FPGA Verification Engineer

Full Job Description

At least 6-9 month project

Key Responsibilities

" System Verilog and UVM FPGA/ASIC verification

" Verification planning & documentation

" Testbench architecture, design & coding

" Simulation analysis and debug

" Coverage analysis and closure

" Provide verification guidance to other team members

YOU MUST HAVE

US Citizenship Only - No Dual Citizenship allowed

Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.