20 Vlsi Design jobs in Sunnyvale

**Company Description**
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
**Job Description**
Join us and jumpstart your career alongside our team of innovators and industry influencers and help shape the future of digital technology with a leading provider of flash memory and storage solutions!
Please note: this posting is not for a specific job opening and by submitting your resume, you are expressing interest in being contacted about one of the following roles at Sandisk:
**Essential duties and responsibilities:**
+ **AI-Enhanced Chip Design** - Design Engineers will be responsible for designing, developing, modifying and evaluating Chip architecture circuit structures for feasibility study of high-performance NAND flash, including new, most advanced 3-dimentional NAND memories. A design engineer will focus on developing technologies related to AI. In this role, you will be part of a multi-disciplinary team of researchers and software developers, working on designing, building, and deploying AI technologies and applications. Familiarity with AI/ML frameworks and the interworking of LLMs are a plus
+ **Analog/Mixed-Signal Design** - NAND Memory Design & Verification Engineers are responsible for designing, developing, modifying, and evaluating analog and mixed-signal integrated circuits (ICs) for high-performance NAND flash, including the most advanced 3-dimensional NAND memories. Engineers in this role will focus on building low-power analog modules such as OPAMPs, voltage regulators, reference generators, and charge pump circuits. You will also contribute to high-voltage word line driver design, sensing operation analysis, and power/ground network optimization. This role offers the opportunity to define chip architecture, floorplan and die size by cross-collaborating with multiple functions including layout, characterization, and silicon validation teams to bring innovative circuit designs from concept to production.
+ **High-Speed PHY and Interface Design -** High-Speed PHY and Interface Design Engineers will be responsible for architecting and implementing custom high-speed PHY and DataPath circuits for NAND interfaces and memory protocols such as DDR3/4/5, LPDDR4/5, GDDR, and HBM. In this role, you will focus on clock recovery, timing budgeting, SI/PI analysis, and analog/digital co-simulation across a wide range of speeds and topologies. The ideal candidate thrives in a multi-disciplinary environment, balancing deep theoretical understanding with practical implementation. Familiarity with Cadence Virtuoso, Synopsys tools, and Verilog/Liberty model development is a plus.
+ **High-Speed Data Path & Circuit Design Engineers** - Circuit Design Engineers in this role will focus on developing and evaluating transistor-level and gate-level architectures for NAND flash memory, including page buffers, sense amplifiers, and high-speed datapath circuits and interface protocol design. You will architect and design digital and/or analog circuits, perform block level and full chip circuit simulations to meet all performance specifications. You will also contribute to RTL design, verification, clock domain crossing (CDC) and Prime time analysis. This role spans the full development lifecycle-from early feasibility and simulation to silicon probing and debug-requiring close collaboration with layout and characterization teams. Proficiency in HSPICE, FINESIM, and Verilog is essential, along with a strong foundation in analog and digital circuit fundamentals.
+ **Physical Design Engineering** - Physical Design Engineers will be responsible for logic synthesis, place and route (P&R), and timing analysis for NAND flash memory chips, ensuring designs meet performance, power, and area (PPA) targets. Engineers in this role will work closely with front-end RTL teams and back-end implementation engineers to perform physical verification, static timing analysis (STA), and tape-out readiness. You will apply deep knowledge of design principles and CAD tools to develop scalable physical design methodologies. Familiarity with scripting (e.g., Python, Perl, TCL) and an understanding of device physics in deep sub-micron technologies are a plus.
**Qualifications**
**Required:**
+ **Master's degree** in Electrical Engineering, Computer Engineering, Computer Science, or related field with a graduation date of **Dec 2024 - May/June 2025**
+ Experience or interest in **3D NAND Flash** and **non-volatile memory**
**Preferred Skills:**
It's helpful if you meet one or more of the following qualifications, but it isn't a requirement.
+ Strong fundamentals in circuit design, particularly analog/mixed-signal and digital
+ Experience with HSPICE, FINESIM, VERILOG, System Verilog, and RTL design
+ Proficiency in troubleshooting, problem-solving, and cross-functional teamwork
+ Excellent communication (written and verbal) and interpersonal skills
+ Eagerness to learn and adapt to new technologies and challenges
+ Self-motivated, collaborative, innovative, and adaptable to a fast-paced environment
**Additional Information**
Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person's gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person's assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal ( " poster. Our pay transparency policy is available here ( .
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
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Posted 57 days ago | Updated 19 hours ago

Overview

On Site

$180,000 - $200,000

Full Time

Skills

DFT, Scan, MBIST, and LBIST

Please contact Abdul on OR email me at

We are seeking a highly skilled Senior SoC/ASIC Physical Design Engineer to lead and drive the physical design activities to successful closure by collaborating closely with RTL and other cross-functional engineering teams. You will be responsible for developing, refining, and implementing cutting-edge flows and methodologies that optimize design performance, power efficiency, and area (PPA). Your expertise will directly contribute to achieving world-class time-to-closure and tapeout with optimal team size and resources.

Responsibilities

1. Develop and Implement PD Flow: Establish a modern physical design (PD) flow utilizing the latest EDA tool fusion and machine learning (ML) techniques to maximize PPA efficiency, optimize resource allocation, and achieve industry-leading time-to-closure and tapeout.
2. End-to-End Physical Design Execution: Perform partition synthesis and physical implementation, including synthesis, floorplanning, power/ground grid generation, place & route, timing, noise, physical verification, electromigration, voltage drop, and signoff checks.
3. Methodology and Automation: Create and refine physical design methodologies and automation scripts to streamline implementation and signoff processes.
4. Cross-Functional Collaboration: Work closely with RTL, DFT, and ASIC design teams to define architectural feasibility, establish timing, power, and area targets, and explore design trade-offs.
5. Drive Design Closure: Utilize an objective, metrics-driven approach to resolve design, timing, and flow issues and ensure predictability in achieving project milestones.
6. Signoff Ownership: Lead signoff closure activities, including static timing analysis (STA), noise analysis, logic equivalency, physical verification, and power integrity (EM/IR).

Basic Qualifications Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (Master's preferred).

• Experience: 10+ years of experience in ASIC/SoC physical design and flow development.
• Technical Proficiency:

Expertise in RTL-to-GDSII physical design and signoff flows.

Strong experience with Synopsys EDA tools, understanding tool capabilities and underlying algorithms.

Proficient in physical design methodologies: synthesis, place & route, STA, formal verification, CDC, and power analysis.

Knowledge of FinFET and deep sub-micron CMOS technologies, including power dissipation, leakage, and dynamic behavior.

Familiarity with DFT, Scan, MBIST, and LBIST methodologies and their impact on physical design.

• Scripting and Automation: Proficient in scripting languages (Python, Tcl, Perl, bash/csh) and automation using Makefiles.
• Analytical Skills: Skilled in extraction and analysis of design parameters, QOR metrics, and implementing voltage scaling (SVS, DVFS) and SRAM split rail architectures.
• Team Collaboration: Proven ability to work collaboratively in dynamic environments, lead design closure activities, and drive execution with a proactive, solution-oriented mindset.

Please contact Abdul on OR email me at

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

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Senior ASIC/VLSI Synthesis and Design Engineer

Get AI-powered advice on this job and more exclusive features.

Pay found in job post

Retrieved from the description.

Base pay range

$185,000.00/yr - $25,000.00/yr

About Celestial AI

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

About The Role

We are looking for a Senior ASIC/VLSI Synthesis and Design Engineer to drive the development of high-performance, low-power digital designs for cutting-edge ASICs and SoCs. This role involves optimizing power, performance, and area while ensuring timing closure, gate-level simulation, and post-silicon validation. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, and power analysis.

If you have a strong background in ASIC/VLSI design, with deep expertise in synthesis, timing closure, DFT, and post-silicon debug, we want to hear from you.

Essential Duties And Responsibilities

• Develop and implement synthesis flows for high-performance, low-power digital designs using industry-standard EDA tools (Genus, Tempus, DC, PrimeTime, Conformal LEC, etc.).
• Define and implement synthesis constraints at block and top levels, ensuring optimal timing closure and gate-level simulation.
• Optimize clock distribution, pipelining, and register balancing for maximum performance.
• Perform Logical Equivalency Checks at all design stages.
• Work closely with DFT teams to integrate scan chains, ATPG, and MBIST into the synthesis flow.
• Perform power analysis and optimization, applying techniques like power gating, clock gating, voltage scaling, and dynamic voltage frequency scaling.
• Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs.
• Collaborate with physical design teams to ensure smooth handoff and timing closure through optimizations, analysis, physical synthesis and ECO implementation as needed.
• Lead design methodology improvements, driving efficiency in RTL-to-GDSII flows.
• Drive post-silicon validation and debug, ensuring successful production ramp-up.
  
  

Qualifications

• Bachelor’s degree with 8+ years of experience, or Master’s degree with 6+ years of experience in Computer Science, Electrical Engineering, Information Technology or a related technical field.
• 8+ years of ASIC/VLSI design experience, focusing on synthesis and timing closure for large scale design in deep submicron technology.
• Expertise in Verilog/SystemVerilog RTL coding and constraint development for synthesis.
• Proficiency in synthesis tools from leading EDA vendors (Cadence, Synopsys, Mentor).
• Experience with gate-level simulation, static timing analysis (STA), and power-aware synthesis.
• Strong post-silicon debug and validation skills, including production bring-up and failure analysis.
• Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimization.
• Strong problem-solving, debugging, and collaboration skills in a fast-paced environment.
  
  

LOCATION : Orange County, CA, or Santa Clara, CA

For California Location:

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000 00 - 225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.

Seniority level

• Seniority level Mid-Senior level

Employment type

• Employment type Full-time

Job function

• Job function Engineering and Information Technology
• Industries Semiconductor Manufacturing

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SRAM Circuit Design Engineer
**Santa Clara, California, United States**
**Hardware**
**Summary**
Posted: **Mar 25, 2025**
Role Number: **200594408**
Do you have a passion for crafting entirely new solutions?
Be a part of a world-class silicon design team which delivered an incredible high performance M1 chip for our Mac line of products and chips for our flagship products (iPhone, iPad, Mac, Airpods, HomePod and Watch).
As part of our Digital Custom Group (DCG), you'll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you'll help design the foundation that allows us to bring customers experiences they've never before envisioned!
This is a highly visible role at the heart of a silicon design effort, making a critical impact delivering products to market quickly. Your designs will strongly influence CPU / GPU / SoC / Neural Engine / Camera designs in Apple's Custom Silicon group.
**Description**
Imagine yourself at the center of our hardware development effort. Where you will collaborate with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new insights, work with a team of hardworking engineers, and implement groundbreaking techniques of Machine Learning, Circuit design in Apple's marquee products like M1 and A14 Bionic.
As an SRAM Circuit Designer for the Digital Custom Group, you will perform the following:
- Design and implement custom digital circuits for SRAM design.
- Work with an extraordinary logic/architecture team to formulate design specifications.
- Define architecture/topologies optimizing for power, timing, area and yield.
- Schematic capture, simulations/analysis, margin verifications.
- Functional equivalency and DFT modeling.
- Work with layout team to create optimal GDS.
- Verify extracted GDS meets design specifications.
- Backend verification, IR/EM
- Write RTL, validate use-cases, verify against design schematics.
- Support post-silicon effort to enable productization.
**Minimum Qualifications**
+ BS and a minimum of 10 years of relevant industry experience.
**Preferred Qualifications**
+ We are looking for applicants with work experience within a SoC design cycle, developing circuits and SRAM/Register File for low power, low voltage and high performance.
+ Knowledge of Cache design/architecture, memory hierarchy is a huge plus.
+ Working knowledge of RTL modeling.
+ Solid understanding of industry-standard design tools.
+ Deep understanding of nanometer device physics, leakage mechanisms, technology interactions with device behavior.
+ Ability to devise experiments and analyze data for silicon debug.
+ Machine Learning algorithms (ML) and scripting is a big plus.
**Pay & Benefits**
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.Learn more about Apple Benefits. ( Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .
Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation.
Apple participates in the E-Verify program in certain locations as required by law.Learn more about the E-Verify program ( .
Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more .
Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more .
Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you're applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines applicable in your area.
It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

**Be visionary**
Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research?
We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.
**Job Description**
The purpose of this job is to design analog circuitry to probe and amplify high speed serial signals for analysis, to measure and characterize analog components or analog subsystems, to document measured performance and compare to design goals, and to review and guide PCB layout to ensure analog circuitry can perform as designed.
**Detailed Duties and Responsibilities:**
**Design analog circuits for probing and amplifying high speed serial data:**
+ Design high speed amplifier subsystems using off the shelf amplifiers
+ Design Bias-T networks with wide bandwidth
+ Design passive equalizers and filters using discrete components
+ Design signal envelope detectors
+ Simulate these designs using Keysight ADS and optimize the component selections as well as layout optimizations
**Measure and characterize HW subcomponents for SI performance:**
+ Measure PCB components using VNA and gather s-parameter data
+ Simulate and publish s-parameter performance to validate if design meets performance target
+ Measure clock jitter with oscilloscope and validate if jitter performance is met
+ Measure power nets with oscilloscope to validate if PDN performance meets expectations
**Perform serdes channel simulations using IBIS AMI models on Keysight ADS software:**
+ Validate Serdes performance can meet target BER
+ Identify optimal TX EQ and RX EQ settings for maximum performance
+ Quantify channel operating margin
**Required Education, Skills and Experience:**
+ Bachelors degree in Electrical Engineering or similar applicable degree
+ 2-5 years minimum experience in an Analog design role
+ Experience with ANSYS HFSS
+ Experience with Keysight ADS
+ Strong interpersonal, organizational and communication skills
+ Team player, persuasive, encouraging, and motivating
+ Open minded, quick learner, creative, likes challenges
**Preferred Qualifications:**
+ Familiar with lab equipment including, oscilloscope, Bert, and VNA
+ Familiarity with at least one high speed interface such as PCI Express, Ethernet or USB
+ Familiarity with channel simulation tools like Seasim or COM
+ Familiarity with Matlab usage for Serdes tuning
+ Masters degree or higher preferred
+ 5-10 years in an Analog Design role
**Salary Range:**
$177,500.00-$236,600.000
**Pay Transparency**
The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, education/training, work experience, key skills, and type of position.
Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.
Teledyne is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other characteristic or non-merit based factor made unlawful by federal, state, or local laws. ?
You may not realize it, but Teledyne enables many of the products and services you use every day **.**
Teledyne provides enabling technologies to sense, transmit and analyze information for industrial growth markets, including aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, energy, medical imaging and pharmaceutical research.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for an experienced engineer to drive the latest innovations in Virtuoso Solution team to improve analog design productivity.
Requirements:- The ideal candidate should have hands on experience with analog mixed signal circuit design development in FinFet nodes , basic layout knowledge is a plus.- Should be hands-on and be comfortable with running simulation and validation tools, creating and analyzing testbench. - Experience with Virtuoso Layout editor and VSE, ADE and Spectre.- Scripting knowledge using skill/python.
- MS/PhD in Electrical Engineering (or related engineering field).
- 3 - 12 years of relevant experience.
Job Location:The preferred location is San Jose, CA.
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.
Additional Jobs ( plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. ? Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Hybrid // Physical Design Engineer-ASICs, SoCs, VLSI

Physical Design Engineer-ASICs, SoCs, VLSI

Full time

Sunnyvale, CA

Job Description:

Key Responsibilities:

Block-Level Physical Design:

• Floorplanning & Partitioning – Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization – Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) – Design and optimize low-skew, high-performance clock networks .
• Routing & DRC Closure – Ensure successful global and detailed routing , meeting design rule constraints.
• Timing Closure – Work on setup/hold timing violations , signal integrity, and cross-talk reduction using static timing analysis (STA) .
• Power & IR Drop Analysis – Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques .

Top-Level Physical Design:

• Chip-Level Floorplanning & Hierarchical Design – Manage top-level layout planning , pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution – Design robust clock trees and power delivery networks (PDN) .
• Integration of IP & Sub-blocks – Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off – Perform final netlist-to-GDSII implementation , addressing physical and electrical verification.
• DFT Integration – Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Information Technology

Industries

IT Services and IT Consulting

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In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

Qualifications

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Responsibilities

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team’s design methodologies and release flows.

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In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we've united two industry leaders to create an optical networking powerhouse-combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;


• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;


• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.


• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;


• Need to support and comply with the team's design methodologies and release flows.

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.


• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.


• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.


• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;


• Must have a good understanding of device physics and the impacts of layout effects;


• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;


• Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;


• Independently resolves issues and conquer design challenges;


• Self-motivated and detail-oriented;


• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years' experience, or Ph.D. in E.E. with 8+ years' experience

Come create the technology that helps the world act together

Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people's lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world.
We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work

What we offer

Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered.

Nokia is committed to inclusion and is an equal opportunity employer

Nokia has received the following recognitions for its commitment to inclusion & equality:

• One of the World's Most Ethical Companies by Ethisphere


• Gender-Equality Index by Bloomberg


• Workplace Pride Global Benchmark

At Nokia, we act inclusively and respect the uniqueness of people. Nokia's employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law.
We are committed to a culture of inclusion built upon our core value of respect.

Join us and be part of a company where you will feel included and empowered to succeed.

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