480 Design For Testability jobs in the United States

**Company Description**
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
**Job Description**
The Memory Technology Group is at the core of the Legacy Sandisk Engineering Organization. We are building a cutting edge 3D memory in our multi-billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost without forgoing quality. The Memory Technology organization is a strategic entity for the company and we are constantly growing. Our group functions as a start-up within Sandisk, and offers a creative, fast paced, entrepreneurial work environment where you'll be at the center of innovation.
We are looking for an experienced Principal Engineer to lead and deliver projects for our Memory Design team. This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and has a great track record for delivering innovative results.
You will need to think creatively about the memory as we do take pride in our craftsmanship. We do work together with all engineering teams to identify and execute on the most disciplined way. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.
Join the Memory Technology Design Team and become a leader of this highly motivated, cooperative, and focused team!
In this position, the individual will be responsible for all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area goals.
ESSENTIAL DUTIES AND RESPONSIBILITIES:
+ RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure
+ Balance design trade-offs with modularity, scalability, power, area, and performance.
+ Interface with internal and external teams/customers to drive necessary technical specifications and features based on individual requirements
+ Participating in Post-Si evaluation and debug
+ Drive cross function support for productization
+ Technical guidance and mentoring of junior engineers
**Qualifications**
**REQUIRED:**
+ MSEE plus 5-10 years of relevant experience
+ Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design
+ Working knowledge of the entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification)
+ Working knowledge of NAND flash memory cell device operations, algorithms for program/read/erase
+ Excellent communication (written and verbal) and interpersonal skills
**PREFERRED:**
+ Experience developing digital circuit designs for low power operating conditions
+ Working knowledge of device physics and process
+ Working knowledge of NAND Flash memory design including Analog, Core, Datapath and IO circuits
+ Proficiency with following Digital design tools
+ Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
+ Static Timing - Synopsys Primetime or Cadence Tempus
+ Place and Route - Synopsys ICC or Cadence Encounter or Innovus
+ Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints)
+ Programming experience in C, C++, Python or Perl
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Self-motivated and self-directed, however, must have demonstrated ability to work well with people. A proven desire to work as a team member, both on the same team and outside of the team. Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadlines. Excellent communication (written and verbal) and interpersonal skills.
**Additional Information**
Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person's gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person's assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal ( " poster. Our pay transparency policy is available here ( .
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
Based on our experience, we anticipate that the application deadline will be **10/17/2025** (3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline.
#LI-KH1
**Compensation & Benefits Details**
+ An employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs.
+ The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future.
+ You will be eligible to participate in Sandisk's Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Sandisk's Standard Terms and Conditions for Restricted Stock Unit Awards.
+ We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan.
+ Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company's sole discretion, consistent with the law.

Our client, a pioneer in cutting-edge semiconductor technology, is seeking a highly skilled Senior Hardware Engineer specializing in VLSI Design to join their esteemed team in San Jose, California, US . This role is instrumental in the design, verification, and implementation of complex integrated circuits (ICs) for next-generation products. The ideal candidate will have a deep understanding of digital logic design, ASIC/FPGA development, and advanced verification methodologies. Responsibilities include RTL design using Verilog/VHDL, synthesis, timing analysis, and performance optimization. You will collaborate with cross-functional teams, including software, firmware, and system architects, to define specifications and ensure seamless integration. A strong grasp of power management techniques, low-power design principles, and exposure to high-speed interfaces is highly desirable. The successful candidate will contribute to architectural decisions, mentor junior engineers, and drive innovation in the VLSI domain. This position offers an excellent opportunity to work on challenging projects at the forefront of technology and contribute to products that will shape the future. You will be involved in the entire design flow, from concept to tape-out and validation.

Key Responsibilities:

• Design, simulate, and verify complex digital logic blocks for ASICs and FPGAs using Verilog/VHDL.
• Perform logic synthesis, static timing analysis, and power analysis.
• Develop and execute comprehensive verification plans and testbenches.
• Collaborate with system architects and software engineers to define and meet hardware requirements.
• Optimize designs for performance, power, and area.
• Participate in architectural discussions and contribute to design reviews.
• Debug and resolve hardware issues during simulation, emulation, and post-silicon validation.
• Mentor junior engineers and contribute to team knowledge sharing.
• Stay updated with the latest advancements in VLSI technology and design methodologies.
• Support the entire IC design flow, from specification to tape-out and bring-up.

Qualifications:

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 7 years of experience in VLSI design and verification.
• Proficiency in RTL design languages (Verilog, VHDL).
• Experience with synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus).
• Strong understanding of static timing analysis (STA) and power analysis tools.
• Experience with verification methodologies (e.g., UVM, OVM) is a plus.
• Knowledge of scripting languages (e.g., Python, Perl, Tcl) for automation.
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and teamwork abilities.
• Ability to thrive in a San Jose, California, US hybrid work environment.

**Company Description**
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
**Job Description**
The Memory Technology Group is at the core of the Legacy Sandisk Engineering Organization. We are building a cutting edge 3D memory in our multiple billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost but on quality. The Memory Technology organization is a strategic entity for the company, and we are growing. Our group functions as a start-up within Sandisk, and offers a creative, fast paced, entrepreneurial work environment where you'll be at the center of Sandisk innovation.
If you thrive in a fast-paced, dynamic environment, are looking to be a part of a team that is developing exciting new processes, and you are eager to take on new opportunities and challenges with a sense of urgency and enthusiasm, then this could be an exciting opportunity for you.
ESSENTIAL DUTIES AND RESPONSIBILITIES:
+ Architect and design circuits at transistor level and gate level for leading-edge 3D NAND flash memory focusing on high-speed datapath circuit design and page buffers.
+ Perform block level and full chip circuit simulations to meet all performance specifications.
+ RTL design, synthesis, static timing analysis and verification in verilog for page buffer and data path control logics.
+ Conduct silicon debugging and evaluation with micro-probing.
+ Collaborate with characterization engineers to fully characterize silicon, and partner with other designers to develop solutions for silicon issues.
+ Generate detailed technical reports and presentations.
**Qualifications**
REQUIRED:
+ Requires MS degree in Electrical Engineering or equivalent with 5 or more years of relevant experience.
+ Knowledge and/or experience in data path design (Nand and/or DRAM)
+ Knowledge in decoding concept and redundancy concept
+ Knowledge and/or experience in Nand page buffer design
+ Knowledge and/or experience in RTL design
+ Knowledge and/or experience in non-volatile memory design (NAND flash memory cell operation in particular) is a big advantage
PREFERRED:
+ Knowledge and/or experience in High speed I/O circuit is a big plus
+ A strong device background and experience with evaluating new process technologies for use in design is preferred.
**Additional Information**
Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person's gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person's assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal ( " poster. Our pay transparency policy is available here ( .
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
Based on our experience, we anticipate that the application deadline will be **10/17/2025** (3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline.
#LI-KH1
**Compensation & Benefits Details**
+ An employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs.
+ The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future.
+ You will be eligible to participate in Sandisk's Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Sandisk's Standard Terms and Conditions for Restricted Stock Unit Awards.
+ We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan.
+ Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company's sole discretion, consistent with the law.

**Company Description**
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
**Job Description**
The Memory Technology Group is at the core of the Legacy SanDisk Engineering Organization which Western Digital owns. We are building a cutting edge 3D memory in our multi-billion dollars Fab. Our memory provides performance, power, and endurance at a lower cost without forgoing quality. The Memory Technology organization is a strategic entity for the company and we are constantly growing. Our group functions as a start-up within Western Digital, and offers a creative, fast paced, entrepreneurial work environment where you'll be at the center of innovation.
We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory Design team. This is a great opportunity for a results-oriented, entrepreneurial individual who knows how to work with non-volatile memory world-class engineers and has a great track record for delivering innovative results.
You will need to think creatively about the memory as we do take pride in our craftsmanship. We do work together with all engineering teams to identify and execute on the most disciplined way. Your success will be measured by your ability to build great designs that deliver innovation that unlock revenue opportunities for the company.
Join the Memory Technology Design Team and become a leader of this highly motivated, cooperative, and focused team!
In this position, the individual will be responsible for all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area goals.
**ESSENTIAL DUTIES AND RESPONSIBILITIES:**
+ RTL design and verification in Verilog, RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT, timing analysis and closure
+ Balance design trade-offs with modularity, scalability, power, area, and performance.
+ Interface with internal and external teams/customers to drive necessary technical specifications and features based on individual requirements
+ Participating in Post-Si evaluation and debug
+ Drive cross function support for productization
+ Technical guidance and mentoring of junior engineers
**Qualifications**
**REQUIRED:**
+ MSEE plus 5 years of relevant experience
+ Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design
+ Working knowledge of the entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification)
+ Working knowledge of NAND flash memory cell device operations, algorithms for program/read/erase
+ Excellent communication (written and verbal) and interpersonal skills
**PREFERRED:**
+ Experience developing digital circuit designs for low power operating conditions
+ Working knowledge of device physics and process
+ Working knowledge of NAND Flash memory design including Analog, Core, Datapath and IO circuits
+ Proficiency with following Digital design tools
+ Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
+ Static Timing - Synopsys Primetime or Cadence Tempus
+ Place and Route - Synopsys ICC or Cadence Encounter or Innovus
+ Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints)
+ Programming experience in C, C++, Python or Perl
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Self-motivated and self-directed, however, must have demonstrated ability to work well with people. A proven desire to work as a team member, both on the same team and outside of the team. Ability to troubleshoot and analyze complex problems. Ability to multi-task and meet deadlines. Excellent communication (written and verbal) and interpersonal skills.
**Additional Information**
Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person's gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person's assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal ( " poster. Our pay transparency policy is available here ( .
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
#LI-KH1

**Company Description**
Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.
**Job Description**
We are looking for highly motivated **Electronic Design Engineers - Physical Design** to join our Memory Technology Design team. This is an exciting opportunity for results-oriented, entrepreneurial individuals to work with world-class non-volatile memory engineers on cutting-edge NAND Flash memory design.
**ESSENTIAL DUTIES AND RESPONSIBILITIES:**
+ Drive all aspects of physical design, including logic synthesis, place and route (P&R), and timing analysis for NAND Flash memory chips
+ Ensure designs meet performance, power, and area (PPA) targets
+ Collaborate closely with front-end RTL teams and back-end implementation engineers on physical verification, static timing analysis (STA), and tape-out readiness
+ Apply deep knowledge of design principles and CAD tools to develop scalable physical design methodologies
Join the Memory Technology Design team and contribute to delivering high-quality, innovative results in next-generation NAND Flash memory.
**Qualifications**
**Required:**
+ **Master's degree** in Electrical Engineering, Computer Engineering, Computer Science, or related field with a graduation date of **Dec 2024 - May/June 2025**
+ Knowledge synthesis, place & route, STA timing analysis and physical verification with EDA CAD tools
**Preferred Skills:**
+ Familiarity with logic & physical design principles.
+ Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL
+ Good understanding of device physics and experience in deep sub-micron technologies Knowledge of Verilog and System Verilog
+ Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated
+ Ability to work well in a team and be productive under aggressive schedules
**Additional Information**
Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person's gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person's assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal ( " poster. Our pay transparency policy is available here ( .
Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.
Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.
#LI-NS1
**Compensation & Benefits Details**
+ An employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs.
+ The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future.
+ You will be eligible to participate in Sandisk's Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Sandisk's Standard Terms and Conditions for Restricted Stock Unit Awards.
+ We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan.
+ Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company's sole discretion, consistent with the law.

Description
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
Key job responsibilities
Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
· Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
· Define, configure and integration SoC Subsystems
· Contribute to the SoC floor planning effort
· Define and develop any necessary support logic
· Configure, instantiate and integrate 3rd party IP blocks
· Understand low power design & the impact of DFT on the blocks
· Perform initial synthesis & timing analysis
· Assist verification team in unit verification including test plan development
· Assist with debug and bring-up
Basic Qualifications
- 5+ years of non-internship professional software development experience
- 5+ years of programming with at least one software programming language experience -
- 5+ years of leading design or architecture (design patterns, reliability and scaling) of new and existing systems experience
- 5+ years of digital design experience, preferably in SoC design and implementation
Preferred Qualifications
- 5+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
- Master's degree in computer science or equivalent
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.
Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $129,800/year in our lowest geographic market up to $212,800/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit . This position will remain posted until filled. Applicants should apply via our internal or external career site.

Description
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
Key job responsibilities
Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
· Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
· Define, configure and integration SoC Subsystems
· Contribute to the SoC floor planning effort
· Define and develop any necessary support logic
· Configure, instantiate and integrate 3rd party IP blocks
· Understand low power design & the impact of DFT on the blocks
· Perform initial synthesis & timing analysis
· Assist verification team in unit verification including test plan development
· Assist with debug and bring-up
Basic Qualifications
- 3+ years of non-internship professional software development experience
- 3+ years of programming with at least one software programming language experience -
- 3+ years of leading design or architecture (design patterns, reliability and scaling) of new and existing systems experience
- 3+ years of digital design experience, preferably in SoC design and implementation
Preferred Qualifications
- 2+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
- Master's degree in computer science or equivalent
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.

Description
Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
Key job responsibilities
RTL Design and development of custom blocks.
Integration of large subsystems
Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure design closure.
Facilitate seamless integration across Firmware, RTL, Platform Software, and Platform Drivers.
Develop Debug tools: RTL Emulation, silicon bring-up, and functional validation.
In this role you will:
· Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets.
· Define, configure and integration SoC Subsystems
· Contribute to the SoC floor planning effort
· Define and develop any necessary support logic
· Configure, instantiate and integrate 3rd party IP blocks
· Understand low power design & the impact of DFT on the blocks
· Perform initial synthesis & timing analysis
· Assist verification team in unit verification including test plan development
· Assist with debug and bring-up
A day in the life
Be part of Project Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
Basic Qualifications
- 8+ years of non-internship professional software development experience
- 8+ years of programming with at least one software programming language experience -
- 8+ years of leading design or architecture (design patterns, reliability and scaling) of new and existing systems experience
- 8+ years of digital design experience, preferably in SoC design and implementation
- Fixed point RTL design
- Filter design (FIR/IIR)
- DSP design
Preferred Qualifications
- 5+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
- Modem wireless or OFDM experience
- Master's degree in computer science or equivalent
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.
Our compensation reflects the cost of labor across several US geographic markets. The base pay for this position ranges from $143,300/year in our lowest geographic market up to $247,600/year in our highest geographic market. Pay is based on a number of factors including market location and may vary depending on job-related knowledge, skills, and experience. Amazon is a total compensation company. Dependent on the position offered, equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package, in addition to a full range of medical, financial, and/or other benefits. For more information, please visit . This position will remain posted until filled. Applicants should apply via our internal or external career site.

**Summary:**
Meta is hiring an ASIC Design Manager within our Infrastructure organization to support the Front-End Design function. We are seeking a technical manager who is a consensus-driven leader, with demonstrated management and leadership experience with comprehensive silicon development expertise, and a proven track record of first-pass silicon success
**Required Skills:**
Manager, ASIC Design Responsibilities:
1. Manage an ASIC front end design team responsible for AI/ML accelerators for data centers. Drive design planning, microarchitecture development and design execution
2. Review micro-architecture and design to meet architecture spec and optimize Power, Performance and Area. Drive key metrics and milestones to meet silicon tape-out schedule
3. Partner with Architecture, SW/FW, Design Verification, Modeling, Emulation, and Post-Silicon Validation teams to achieve high quality design
4. Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts
5. Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's long term objectives
6. Identify candidates, hire, schedule, support and train a team of ASIC engineers in order to develop products on time and on budget
7. Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers
8. Support engineering teams to define, debug, implement and deliver total solutions around purpose-built ASICs
9. Define, implement and maintain key performance indicators (KPI) for areas of responsibility
10. Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors
**Minimum Qualifications:**
Minimum Qualifications:
11. B.S. or M.S. degree in Computer Engineering or Electrical Engineering
12. 12+ years of experience managing ASIC/SoC design teams at the Director or Manager level and working across multiple projects and adjusting priorities in partnership with stakeholders
13. 3+ years of experience as a People Manager, with a proven track record in strategic leadership, including planning and implementation for risk management and growth, recruiting, managing, and performance-managing technical teams, and utilizing data-driven decision-making skills to develop and manage requirements
14. Experience with multiple successful ASIC tape-outs. Track record of first-pass success
15. Experienced with interpreting functional specs and developing architecture, microarchitecture and logic design. Experience working with synthesis, timing and design constraints
16. Experience with SoC bring-up and post-silicon validation
17. Clear understanding of state-of-the-art design flows, design and verification methodologies
**Preferred Qualifications:**
Preferred Qualifications:
18. Demonstrated understanding of ASICs and systems for AI/ML and high-performance networking
19. Experience optimizing systems for large-scale AI/ML workloads is highly valued
**Public Compensation:**
$212,000/year to $291,000/year + bonus + equity + benefits
**Industry:** Internet
**Equal Opportunity:**
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at