3,012 Hardware Verification jobs in the United States
Lead Hardware Verification Engineer
45202 Cincinnati, Ohio
$140000 Annually
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Our client is seeking an experienced and visionary Lead Hardware Verification Engineer to join their cutting-edge R&D team in Cincinnati, Ohio, US . This is a critical leadership position responsible for architecting and executing comprehensive verification strategies for complex System-on-Chip (SoC) designs. You will lead a team of talented engineers, mentor junior members, and drive the verification methodology forward. The ideal candidate will have a deep understanding of digital design principles, verification languages (e.g., SystemVerilog), and simulation/emulation environments. Responsibilities include developing and maintaining the verification environment, creating robust testbenches, defining verification plans, and ensuring complete functional coverage of the design. You will work closely with RTL design engineers, architects, and system engineers to resolve issues and ensure silicon success. Experience with UVM (Universal Verification Methodology) is essential. The ability to debug complex hardware issues at the IP and SoC level is paramount. This role requires strong analytical and problem-solving skills, excellent leadership qualities, and the ability to communicate technical information effectively to both technical and non-technical audiences. A Master's or Ph.D. in Electrical Engineering or a related field is preferred. This is a hands-on leadership role where you will be instrumental in delivering next-generation silicon products. You will be responsible for the sign-off of verification on key IPs and the overall SoC. We are looking for someone who is proactive, detail-oriented, and passionate about pushing the boundaries of hardware verification. The successful candidate will play a key role in defining the future verification infrastructure and processes within the company. This position offers an exciting opportunity to work on challenging projects with a significant impact on the company's success.
Responsibilities:
Responsibilities:
- Lead and mentor a team of hardware verification engineers.
- Develop and maintain sophisticated verification environments using SystemVerilog and UVM.
- Create detailed verification plans and ensure adherence to coverage goals.
- Design and implement reusable verification components and testbenches.
- Debug functional and performance issues at IP and SoC levels.
- Collaborate with RTL design and system engineers to achieve first-pass silicon success.
- Drive adoption of advanced verification methodologies and tools.
- Perform code reviews and provide constructive feedback to team members.
- Track and report verification progress to project management.
- Master's or Ph.D. in Electrical Engineering or related field.
- 8+ years of experience in hardware verification.
- Proven experience leading verification teams.
- Expertise in SystemVerilog, UVM, and simulation/emulation tools.
- Strong understanding of digital logic design and computer architecture.
- Excellent debugging and problem-solving skills.
- Strong communication and interpersonal skills.
- Experience with scripting languages (e.g., Python, Perl) is a plus.
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0
Senior Hardware Verification Engineer
50309 Des Moines, Iowa
$120000 Annually
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Posted 1 day ago
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Our client, a cutting-edge semiconductor design firm located in Des Moines, Iowa, US , is seeking an experienced Senior Hardware Verification Engineer to join their innovative design team. This role is critical in ensuring the functional correctness and performance of complex digital hardware designs through rigorous verification methodologies. You will be responsible for developing test plans, writing verification components, and executing simulations to identify and resolve design flaws. The ideal candidate possesses a strong understanding of Verilog/SystemVerilog, UVM (Universal Verification Methodology), and enjoys tackling challenging verification problems in a fast-paced environment. This position offers a unique opportunity to work on next-generation technologies and contribute significantly to the success of groundbreaking products.
Responsibilities:
Responsibilities:
- Develop comprehensive verification plans and strategies for complex digital ASIC designs.
- Write and maintain high-quality verification code using SystemVerilog and industry-standard methodologies like UVM.
- Create test benches, constrained-random test cases, and directed tests to achieve high coverage metrics.
- Simulate and debug hardware designs, identifying and resolving functional and performance issues.
- Collaborate closely with RTL designers to understand design specifications and ensure proper implementation.
- Develop assertions and coverage models to effectively measure verification completeness.
- Participate in design reviews and provide feedback from a verification perspective.
- Analyze simulation results, identify root causes of failures, and work with design engineers to resolve bugs.
- Stay up-to-date with the latest verification techniques, tools, and methodologies.
- Mentor junior verification engineers and contribute to team knowledge sharing.
- Contribute to the development and improvement of verification flows and infrastructure.
- Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in hardware verification, with a focus on ASICs or FPGAs.
- Strong proficiency in Verilog and SystemVerilog.
- Proven experience with UVM (Universal Verification Methodology).
- Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor QuestaSim).
- Familiarity with scripting languages such as Python or Perl for automation.
- Solid understanding of digital logic design principles and computer architecture.
- Experience with coverage-driven verification techniques.
- Excellent problem-solving, analytical, and debugging skills.
- Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.
- Experience with low-power verification techniques is a plus.
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1
Lead Hardware Verification Engineer
23456 Virginia Beach, Virginia
$130000 Annually
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Posted 4 days ago
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Job Description
Our client, a cutting-edge technology firm specializing in advanced semiconductor design, is looking for an experienced Lead Hardware Verification Engineer to join their innovative team in Virginia Beach, Virginia, US . This is a critical role responsible for the verification of complex digital designs, ensuring the highest levels of quality and performance. You will lead a team of verification engineers, guiding them through the entire verification lifecycle, from test plan development to final sign-off. The ideal candidate will have a deep understanding of SystemVerilog, UVM, and various verification methodologies. You will be instrumental in developing and executing comprehensive verification strategies for next-generation System-on-Chips (SoCs). This includes defining coverage goals, creating robust test benches, and implementing advanced verification techniques such as formal verification and constrained-random simulation. You will also be responsible for debugging complex hardware issues, collaborating closely with RTL design teams to resolve functional bugs, and contributing to the continuous improvement of verification flows and methodologies. This role requires strong analytical skills, excellent problem-solving abilities, and a proven track record of successfully delivering complex verification projects. As a lead, you will mentor junior engineers, foster a collaborative team environment, and contribute to the technical direction of the verification group. The hybrid work model allows for focused independent work and in-person collaboration with design teams and management in our Virginia Beach, Virginia, US office.
Responsibilities:
Responsibilities:
- Lead the hardware verification efforts for complex digital designs (SoCs, IP blocks).
- Develop and execute comprehensive verification plans and test strategies using UVM and SystemVerilog.
- Define verification goals, coverage metrics, and ensure high-quality verification closure.
- Create and maintain sophisticated test benches, including directed and constrained-random tests.
- Debug complex hardware issues, working closely with RTL design engineers to resolve bugs efficiently.
- Utilize formal verification techniques to augment simulation-based verification.
- Mentor and guide junior verification engineers, fostering a collaborative team environment.
- Contribute to the development and improvement of verification methodologies and flows.
- Interface with cross-functional teams, including software, firmware, and system architects.
- Stay current with the latest verification technologies and industry best practices.
- Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 8 years of experience in ASIC or FPGA verification.
- Extensive experience with SystemVerilog and the Universal Verification Methodology (UVM).
- Proven experience leading verification teams and managing complex projects.
- Strong understanding of digital design principles and computer architecture.
- Proficiency in scripting languages (e.g., Python, Perl) for automation.
- Experience with formal verification tools and methodologies is a plus.
- Excellent analytical, problem-solving, and communication skills.
- Experience in a hybrid work environment, demonstrating self-discipline and collaboration.
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2
Senior Hardware Verification Engineer
19102 William Penn Annex West, Pennsylvania
$135000 Annually
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Posted 7 days ago
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Job Description
Our client, a cutting-edge technology firm specializing in advanced semiconductor design, is looking for a highly experienced Senior Hardware Verification Engineer to join their fully remote team. This is an exceptional opportunity to work on the forefront of technological innovation from the comfort of your own home. You will be instrumental in ensuring the functional correctness and performance of complex digital hardware designs through rigorous verification methodologies. As a remote-first organization, we provide a collaborative virtual environment, robust communication tools, and a supportive culture that empowers our engineers to excel.
Responsibilities:
Responsibilities:
- Develop and implement comprehensive verification strategies and test plans for complex System-on-Chip (SoC) and ASIC designs.
- Design, write, and debug verification environments using industry-standard methodologies (e.g., UVM, OVM, VMM) and languages (e.g., SystemVerilog, Verilog).
- Create reusable verification IP, assertions, and testbenches to accelerate the verification process.
- Perform functional verification, performance verification, and coverage analysis to ensure design quality and completeness.
- Collaborate closely with RTL design engineers to understand design specifications and identify potential issues early in the design cycle.
- Analyze simulation results, debug failing tests, and work with designers to resolve bugs effectively.
- Develop and maintain verification infrastructure, including simulators, debug tools, and scripting environments.
- Contribute to the improvement of verification methodologies and tools within the engineering team.
- Track and report on verification progress, coverage metrics, and bug status to management and project teams.
- Mentor junior verification engineers and share knowledge on best practices.
- Stay current with the latest advancements in hardware verification technologies and methodologies.
- Participate in design reviews and provide valuable feedback from a verification perspective.
- Work effectively in a distributed team environment, utilizing collaboration tools for communication and task management.
- Ensure adherence to coding standards and best practices for verification code.
- Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 7 years of experience in digital hardware verification.
- Extensive experience with SystemVerilog and object-oriented verification methodologies like UVM is mandatory.
- Strong proficiency in scripting languages such as Python, Perl, or TCL.
- In-depth knowledge of simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa, Verdi).
- Experience with formal verification techniques is a plus.
- Familiarity with synthesis tools and FPGA flows is beneficial.
- Excellent problem-solving and analytical skills.
- Strong communication and collaboration skills, with the ability to work effectively in a remote team.
- Demonstrated ability to take ownership of verification tasks and deliver high-quality results.
- Experience with SoC/ASIC design and architecture.
- A proactive and self-motivated individual with a passion for cutting-edge technology.
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3
Principal Hardware Verification Engineer
32201 Riverview, Florida
$160000 Annually
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Posted 7 days ago
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Job Description
Our client is seeking a highly experienced Principal Hardware Verification Engineer to join their cutting-edge semiconductor design team. This is a fully remote position, offering the opportunity to work on challenging and impactful projects from anywhere. You will be responsible for leading verification efforts for complex ASIC designs, developing robust verification methodologies, and ensuring the functional correctness and performance of state-of-the-art hardware. As a principal engineer, you will play a critical role in mentoring junior engineers, driving innovation in verification techniques, and collaborating with design and system teams to achieve first-time silicon success.
Key Responsibilities:
This is a remote-first role, requiring excellent self-management, strong communication skills, and the ability to work collaboratively in a distributed team environment. You will have the autonomy to shape your work and contribute to the success of groundbreaking technologies. The ideal candidate is a visionary leader with a deep understanding of digital logic design, verification principles, and industry-standard tools.
Qualifications:
Key Responsibilities:
- Define and drive the verification strategy for complex digital IP and SoC designs.
- Develop and maintain the verification environment using SystemVerilog, UVM, and other advanced methodologies.
- Create comprehensive test plans, constrained-random testbenches, and coverage models.
- Architect and implement complex verification IP and checkers.
- Lead the debug process for functional and performance issues, working closely with the design team.
- Define and track functional coverage, code coverage, and assertion coverage metrics.
- Develop and maintain reusable verification components and infrastructure.
- Perform logic synthesis and static timing analysis reviews.
- Mentor and guide junior verification engineers.
- Evaluate and adopt new verification technologies and methodologies.
- Collaborate with architecture and design teams to refine specifications and ensure design for verification.
- Participate in architectural reviews and provide critical feedback on design complexity and testability.
- Communicate verification status, risks, and results effectively to management and project teams.
This is a remote-first role, requiring excellent self-management, strong communication skills, and the ability to work collaboratively in a distributed team environment. You will have the autonomy to shape your work and contribute to the success of groundbreaking technologies. The ideal candidate is a visionary leader with a deep understanding of digital logic design, verification principles, and industry-standard tools.
Qualifications:
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of experience in hardware verification of complex ASICs/SoCs.
- Expertise in SystemVerilog, UVM, and object-oriented programming principles.
- Proficiency in scripting languages such as Python, Perl, or Tcl.
- Strong understanding of digital logic design, computer architecture, and static timing analysis.
- Experience with formal verification methodologies is a plus.
- Proven track record of leading verification efforts and delivering complex designs.
- Excellent problem-solving, debug, and analytical skills.
- Strong communication and interpersonal skills for effective collaboration in a remote setting.
- Experience with industry-standard simulation and synthesis tools.
- Deep understanding of processor architectures (e.g., ARM, RISC-V) is highly desirable.
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4
Senior Hardware Verification Engineer
95124 San Jose, California
$150000 Annually
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Posted 7 days ago
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Job Description
Our client, a leading innovator in semiconductor technology, is seeking a highly accomplished Senior Hardware Verification Engineer to join their cutting-edge team in **San Jose, California, US**. This role is critical to the development and validation of next-generation microprocessors and complex integrated circuits. You will be responsible for developing and implementing comprehensive verification strategies, creating testbenches using SystemVerilog and UVM, and executing simulation test plans to ensure the functional correctness and performance of our client's designs. Key responsibilities include defining verification requirements, architecting reusable verification IP, performing pre-silicon functional verification, debugging failures, and collaborating closely with RTL design engineers. The ideal candidate will have a strong foundation in digital logic design, computer architecture, and modern verification methodologies. A minimum of 7 years of hands-on experience in hardware verification is required, with a proven track record of successfully verifying complex ASIC designs. Expertise in SystemVerilog, UVM, and scripting languages (e.g., Perl, Python) is essential. Familiarity with formal verification techniques and gate-level simulations is a plus. Excellent problem-solving skills, attention to detail, and the ability to work effectively in a fast-paced, collaborative R&D environment are paramount. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required. This position requires you to be on-site at our **San Jose, California, US** facility, offering a challenging and rewarding career opportunity within a highly innovative company dedicated to pushing the boundaries of technology.
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5
Senior Hardware Verification Engineer
21201 Baltimore, Maryland
$135000 Annually
WhatJobs
Posted 7 days ago
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Job Description
Our client is seeking a highly experienced Senior Hardware Verification Engineer to join their innovative and fully remote engineering team. This is an exciting opportunity to contribute to the development of state-of-the-art silicon designs from the comfort of your home office, with a focus on ensuring the functional correctness and performance of complex digital circuits. You will be instrumental in developing and executing comprehensive verification plans, creating testbenches, and debugging design issues to ensure first-pass silicon success. The ideal candidate will possess deep expertise in hardware description languages (HDLs), verification methodologies (e.g., UVM, OVM), and simulation tools. This role requires strong analytical skills, meticulous attention to detail, and the ability to collaborate effectively with remote design teams. While the position is fully remote, occasional travel may be required for critical project milestones or team events.
Key responsibilities include:
Qualifications:
Key responsibilities include:
- Developing and implementing robust verification strategies and plans for complex ASIC designs.
- Creating directed and random test cases to ensure thorough coverage of design specifications.
- Developing and maintaining verification environments using HDLs (Verilog, VHDL) and SystemVerilog.
- Utilizing advanced verification methodologies such as UVM/OVM for efficient testbench development.
- Simulating designs and analyzing results to identify and debug functional errors.
- Collaborating closely with RTL design engineers to resolve verification issues.
- Defining and tracking key verification metrics, including code and functional coverage.
- Participating in design reviews and providing feedback from a verification perspective.
- Mentoring junior verification engineers and sharing best practices.
- Evaluating and recommending new verification tools and methodologies.
- Contributing to the development of IP blocks and system-level verification.
Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 7 years of experience in hardware verification of complex digital ASICs.
- Proven expertise in SystemVerilog, Verilog, and VHDL.
- Extensive experience with verification methodologies like UVM, OVM, or similar.
- Proficiency with industry-standard simulation and waveform analysis tools.
- Strong understanding of computer architecture and digital logic design.
- Experience with scripting languages (e.g., Python, Perl, Tcl) for automation.
- Excellent debugging and problem-solving skills.
- Ability to work independently and manage complex verification tasks in a remote environment.
- Strong communication and collaboration skills for interacting with global teams.
- Familiarity with FPGA prototyping is a plus.
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6
Senior Hardware Verification Engineer
60601 Chicago, Illinois
$145000 Annually
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Posted 7 days ago
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Job Description
Our client, a global leader in technology innovation, is seeking an accomplished Senior Hardware Verification Engineer to join their prestigious engineering team in Chicago, Illinois. This role is pivotal in ensuring the design integrity and functionality of cutting-edge semiconductor products.
Responsibilities:
Responsibilities:
- Develop and execute comprehensive verification plans and methodologies for complex digital designs (ASICs/SoCs).
- Create and maintain reusable verification environments using industry-standard simulation and emulation tools.
- Write and debug complex test benches, directed tests, and constrained-random test programs.
- Collaborate closely with RTL design engineers to understand design specifications and identify potential issues.
- Perform functional coverage analysis and drive verification closure.
- Debug simulation failures and work with design teams to resolve issues in a timely manner.
- Utilize formal verification techniques where appropriate to ensure design correctness.
- Develop and maintain scripts for automation of verification tasks.
- Stay current with the latest advancements in verification methodologies, tools, and technologies.
- Mentor junior verification engineers and contribute to the team's technical growth.
- Participate in architectural reviews and provide feedback on design for verifiability.
- Ensure adherence to project schedules and deliver verification results on time.
- Contribute to the continuous improvement of the verification process and best practices.
- Work with system-level verification and emulation teams to ensure seamless integration.
- Document verification strategies, test plans, and test results thoroughly.
- Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
- Minimum of 7 years of hands-on experience in hardware verification of complex digital designs (ASICs/SoCs).
- Proficiency in SystemVerilog, Verilog, or VHDL is essential.
- Extensive experience with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor QuestaSim).
- Strong understanding of verification methodologies such as UVM, OVM, or VMM.
- Experience with scripting languages (e.g., Python, Perl, Tcl) for automation.
- Familiarity with hardware description languages and digital design principles.
- Excellent problem-solving and debugging skills.
- Strong communication and teamwork abilities.
- Experience with formal verification tools and techniques is a plus.
- Familiarity with CPU architectures, interconnect fabrics, or memory controllers is desirable.
- Ability to work independently and manage priorities effectively.
- Experience in the Chicago, Illinois technology sector is an advantage.
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7
Senior Hardware Verification Engineer
49503 Grand Rapids, Michigan
$135000 Annually
WhatJobs
Posted 7 days ago
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Job Description
Our client is a cutting-edge semiconductor design company looking for a highly skilled Senior Hardware Verification Engineer to join our fully remote engineering team. This role is critical in ensuring the functional correctness and quality of our complex System-on-Chip (SoC) designs before tape-out. You will be responsible for developing, implementing, and executing advanced verification strategies, methodologies, and test plans using state-of-the-art tools and techniques.
Key Responsibilities:
Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field. A minimum of 7 years of experience in hardware verification for ASICs/SoCs is required. Strong expertise in SystemVerilog, UVM, and RTL simulation/debugging tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Proven experience in developing complex verification environments from scratch. Deep understanding of digital design principles and computer architecture. Experience with scripting languages (e.g., Python, Perl) for automation. Familiarity with formal verification techniques is a plus. Excellent problem-solving, analytical, and debugging skills. Strong communication and collaboration skills, with the ability to work effectively in a distributed team environment. This is an exceptional opportunity for an experienced verification engineer to contribute to groundbreaking semiconductor technologies while enjoying the flexibility of a remote work arrangement.
Key Responsibilities:
- Develop and maintain comprehensive verification plans and strategies for complex digital designs (SoCs, IPs).
- Design, implement, and debug verification environments using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard languages and methodologies.
- Create directed and constrained-random testbenches, test cases, and verification IP.
- Develop coverage models and metrics to ensure thorough verification of design functionality.
- Analyze simulation results, debug failures, and identify root causes of design bugs.
- Collaborate closely with RTL design engineers to understand design specifications and resolve verification issues.
- Participate in design reviews and provide feedback on testability and verification completeness.
- Explore and adopt new verification technologies and methodologies to improve efficiency and effectiveness.
- Assist in architectural definition and system-level verification.
- Mentor junior verification engineers and contribute to team knowledge sharing.
- Manage version control and tool flows for verification projects.
- Work with cross-functional teams, including firmware and software engineers, to ensure complete system validation.
- Document verification environments, test plans, and test results.
- Contribute to the development of reusable verification components and infrastructure.
- Ensure adherence to company verification standards and best practices.
Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field. A minimum of 7 years of experience in hardware verification for ASICs/SoCs is required. Strong expertise in SystemVerilog, UVM, and RTL simulation/debugging tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa). Proven experience in developing complex verification environments from scratch. Deep understanding of digital design principles and computer architecture. Experience with scripting languages (e.g., Python, Perl) for automation. Familiarity with formal verification techniques is a plus. Excellent problem-solving, analytical, and debugging skills. Strong communication and collaboration skills, with the ability to work effectively in a distributed team environment. This is an exceptional opportunity for an experienced verification engineer to contribute to groundbreaking semiconductor technologies while enjoying the flexibility of a remote work arrangement.
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8
Remote Senior Hardware Verification Engineer
73101 Oklahoma City, Oklahoma
$125000 Annually
WhatJobs
Posted 5 days ago
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Job Description
Our client is seeking a highly experienced Senior Hardware Verification Engineer to join their innovative team in a fully remote capacity, supporting operations that extend to Oklahoma City, Oklahoma, US . This position is critical for ensuring the functional correctness and quality of complex System-on-Chip (SoC) designs. You will be responsible for developing and executing verification strategies, writing testbenches, and driving the verification closure of cutting-edge hardware projects. The ideal candidate possesses a strong analytical mindset, a deep understanding of digital design principles, and expertise in UVM or similar verification methodologies.
Responsibilities:
Responsibilities:
- Develop and implement comprehensive verification plans for complex digital IPs and SoCs.
- Design and build reusable verification components and testbenches using SystemVerilog and UVM.
- Create directed and constrained-random test cases to achieve high functional coverage.
- Define and track key verification metrics, including code and functional coverage.
- Debug simulation failures, identify root causes, and work closely with design engineers to resolve issues.
- Utilize formal verification techniques where appropriate to complement simulation-based verification.
- Collaborate with cross-functional teams, including design, architecture, and firmware engineers.
- Review design specifications and micro-architectural documents to ensure comprehensive testability.
- Develop and maintain simulation environments and scripts.
- Contribute to the continuous improvement of verification methodologies and tools.
- Mentor junior engineers and provide technical guidance.
- Document verification strategies, test plans, and results thoroughly.
- Participate in technical discussions and contribute to design reviews.
- Stay up-to-date with the latest advancements in hardware verification technologies.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 7+ years of experience in hardware verification for ASICs or FPGAs.
- Proficiency in SystemVerilog for verification.
- Extensive experience with the Universal Verification Methodology (UVM).
- Strong understanding of digital design principles, computer architecture, and common bus protocols (e.g., AXI, AHB).
- Experience with scripting languages such as Perl, Python, or Tcl.
- Familiarity with simulation tools (e.g., VCS, Questa, Xcelium).
- Experience in coverage-driven verification and metric analysis.
- Excellent problem-solving, debugging, and analytical skills.
- Strong communication and collaboration skills, suitable for a remote team environment.
- Ability to work independently and manage priorities effectively.
- Experience with formal verification is a plus.
- Knowledge of C/C++ for testbench development is also beneficial.
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9