20 High Speed Design jobs in the United States

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**Job Description:**
High Speed RTL Design Engineer
Qualifications include:
+ MS or PhD in Electrical Engineering or Computer Engineering with 10+ years of experience in RTL design.
+ Proficient with Verilog-HDL/System Verilog coding.
+ Proficient with front end tools such as NCVerilog, NCSIM/VCS, Simvision, Lint, Spyglass.
+ Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.
+ Experience with digital design for data converters: ADCs and DACs with understanding of relevant DSP principles such as sampling, noise shaping and filtering.
+ Experience in synthesis, CDC, static timing analysis.
+ Exposure to SDF annotated simulations with good understanding of parasitic delays.
+ Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
+ Strong analytical thinking and problem-solving skills with excellent attention to details.
+ Must be organized, self-motivated and able to work effectively across internal and end customers teams.
+ Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
Highly Desired Qualifications:
- Implementation of digital processing stages for oversampled bitstream processing including decimation and interpolation
- Digital filter design including CIC, FIR and IIR architectures
- Digital delta sigma loop design for the digital frontend of delta sigma DACs
- Understanding of micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART.
- Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
- Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be helpful.
- Willing to work in a multifunctional role.
- Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.
- Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.
- Excellent time and task management, and interpersonal skills.
**Additional Job Description:**
**Compensation and Benefits**
The annual base salary range for this position is $141,000 - $225,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.**
**If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**
Welcome! Thank you for your interest in Broadcom!
We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.
For more information please visit our video library ( and check out our Connected by Broadcom ( series.
Follow us on Linked In Broadcom Inc ( .

**Please Note:**
**1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)**
**2. If you already have a Candidate Account, please Sign-In before you apply.**
**Job Description:**
**Broadcom is looking for a Master RTL Designer. In this highly visible role, you will be responsible for leading the design and development of highly integrated SerDes solutions for the next generation of AI connectivity.**
**Qualifications include:**
+ **MS or PhD in Electrical Engineering or Computer Engineering with 13+ years of experience in front end digital design for serial high-speed data center networking applications.**
+ **Experience as a Lead digital designer for chip and platform for high bandwidth/high speed SerDes applications in advanced modulation formats.**
+ **Experience in integrating the front end design with DV for test methodologies and verification. Providing guidelines for GLS, DFT & Verification.**
+ **Hands on experience in providing guidelines for design constraints generation and evaluating processes for backend development, floorplan, guidelines for Place and Route.**
+ **Evaluating timing signoff, verification and IP Integration and system level verification.**
+ **Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.**
+ **Deep understanding of high-speed optical/electrical interconnect architectures such as 200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.**
+ **Experience in driving SOC level front end design specifications and other documentation in a clear and concise fashion.**
+ **Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule.**
+ **Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development.**
+ **Strong analytical thinking and problem-solving skills with excellent attention to details.**
+ **Must be organized, self-motivated and able to work effectively across internal and end customers teams.**
+ **Must have prior experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.**
**Highly Desired Qualifications:**
+ **System knowledge of current generation and next generation of silicon photonics-based transceiver architectures and standards.**
+ **Good understanding of advanced packaging (2.5D / 3D) architectures.**
+ **Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.**
+ **Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.**
+ **Excellent time and task management, and interpersonal skills.**
+ **Willingness to travel when required.**
**Additional Job Description:**
**Compensation and Benefits**
The annual base salary range for this position is $163,000 - $262,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.**
**If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**
Welcome! Thank you for your interest in Broadcom!
We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.
For more information please visit our video library ( and check out our Connected by Broadcom ( series.
Follow us on Linked In Broadcom Inc ( .

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

Qualifications

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

Responsibilities

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team’s design methodologies and release flows.

#J-18808-Ljbffr

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we've united two industry leaders to create an optical networking powerhouse-combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;


• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;


• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.


• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;


• Need to support and comply with the team's design methodologies and release flows.

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.


• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.


• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.


• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;


• Must have a good understanding of device physics and the impacts of layout effects;


• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;


• Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;


• Independently resolves issues and conquer design challenges;


• Self-motivated and detail-oriented;


• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years' experience, or Ph.D. in E.E. with 8+ years' experience

Come create the technology that helps the world act together

Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people's lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world.
We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work

What we offer

Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered.

Nokia is committed to inclusion and is an equal opportunity employer

Nokia has received the following recognitions for its commitment to inclusion & equality:

• One of the World's Most Ethical Companies by Ethisphere


• Gender-Equality Index by Bloomberg


• Workplace Pride Global Benchmark

At Nokia, we act inclusively and respect the uniqueness of people. Nokia's employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law.
We are committed to a culture of inclusion built upon our core value of respect.

Join us and be part of a company where you will feel included and empowered to succeed.

#J-18808-Ljbffr

CA Pay Range (Annual):

$161,000.00 - $299,000.00

At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.

Infinera also offers paid leave, medical,

dental, and vision coverage, 401(k),

life, and disability insurance to eligible employees.

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production.

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry.

Essential Functions and Key Responsibilities:

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team’s design methodologies and release flows.

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience

#LI-SR2

“This position requires direct or indirect access to certain confidential information, hardware, software, technology, or technical information (referred to here as “Export-Controlled Information”) controlled under the U.S. International Traffic in Arms Regulations (ITAR) and/or the U.S. Export Administration Regulations (EAR). All personnel in this position must be eligible to or be able to obtain authorization from the appropriate agency to access applicable Export-Controlled Information. The U.S. Department of Commerce currently requires a foreign person with a most recent citizenship or permanent residency of Sudan, Ukraine, or a country currently designated in Country Group D:1, E:1 or E:2 (Supplement No. 1 to Part 740, Title 15) to have an export control license to access our Export-Controlled Information, unless they meet certain exemptions provided under U.S. export control laws and regulations. The list of applicable countries in Country Group D:1, E:1 or E:2 may be updated by the U.S. government from time to time. The current processing time for an export control license is approximately 4 to 6 months.

Your employment or engagement with Infinera shall be contingent on verifying your eligibility or requirement for obtaining a necessary license and/or authorization from the appropriate agency. You will be required to provide certain information for export control compliance assessment purposes, and your information will be reviewed by Infinera's hiring and export control teams to ensure compliance with the U.S. export control laws and regulations. Infinera will collect necessary documents (such as proof of citizenship etc.) to assess license/authorization requirements if you are offered and accept the position.”

Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.

#J-18808-Ljbffr

Principal High Speed Mixed Signal Circuit Design Engineer

Join to apply for the Principal High Speed Mixed Signal Circuit Design Engineer role at Infinera

Continue with Google Continue with Google

Principal High Speed Mixed Signal Circuit Design Engineer

3 days ago Be among the first 25 applicants

Join to apply for the Principal High Speed Mixed Signal Circuit Design Engineer role at Infinera

CA Pay Range (Annual)

$161,000.00 - $99,000.00

At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company’s incentive plans, the Company’s financial performance, and/or individual employee job performance.

Infinera also offers paid leave, medical,

dental, and vision coverage, 401(k),

life, and disability insurance to eligible employees.

The successful candidate shall possess the capability to design and analyze high speed, high performance analog / mixed signal circuits, including data converters, PLLs, and SERDES, in advanced CMOS FinFET technologies. She or he shall bring the design all the way to production.

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users.

If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera!

Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry.

Essential Functions And Key Responsibilities

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team’s design methodologies and release flows.
  
  

Mandatory Knowledge/Skills/Abilities

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.
  
  

Preferred Knowledge/Skill/Abilities

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.
  
  

Education And Experience Requirements

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience
  
  

“This position requires direct or indirect access to certain confidential information, hardware, software, technology, or technical information (referred to here as “Export-Controlled Information”) controlled under the U.S. International Traffic in Arms Regulations (ITAR) and/or the U.S. Export Administration Regulations (EAR). All personnel in this position must be eligible to or be able to obtain authorization from the appropriate agency to access applicable Export-Controlled Information. The U.S. Department of Commerce currently requires a foreign person with a most recent citizenship or permanent residency of Sudan, Ukraine, or a country currently designated in Country Group D:1, E:1 or E:2 (Supplement No. 1 to Part 740, Title 15) to have an export control license to access our Export-Controlled Information, unless they meet certain exemptions provided under U.S. export control laws and regulations. The list of applicable countries in Country Group D:1, E:1 or E:2 may be updated by the U.S. government from time to time. The current processing time for an export control license is approximately 4 to 6 months.

Your employment or engagement with Infinera shall be contingent on verifying your eligibility or requirement for obtaining a necessary license and/or authorization from the appropriate agency. You will be required to provide certain information for export control compliance assessment purposes, and your information will be reviewed by Infinera's hiring and export control teams to ensure compliance with the U.S. export control laws and regulations. Infinera will collect necessary documents (such as proof of citizenship etc.) to assess license/authorization requirements if you are offered and accept the position.”

Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.

Seniority level

• Seniority level Mid-Senior level

Employment type

• Employment type Full-time

Job function

• Job function Engineering and Information Technology
• Industries Telecommunications

Referrals increase your chances of interviewing at Infinera by 2x

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We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

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Principal High Speed Mixed Signal Circuit Design Engineer

Join to apply for the Principal High Speed Mixed Signal Circuit Design Engineer role at Nokia

Principal High Speed Mixed Signal Circuit Design Engineer

2 days ago Be among the first 25 applicants

Join to apply for the Principal High Speed Mixed Signal Circuit Design Engineer role at Nokia

Job Description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The

Job Description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

How You Will Contribute And What You Will Learn

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team’s design methodologies and release flows.
  
  

Key Skills And Experience

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.
  
  

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.
  
  

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience
  
  

About Us

Come create the technology that helps the world act together

Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world.

We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work

What we offer

Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered.

Nokia is committed to inclusion and is an equal opportunity employer

Nokia has received the following recognitions for its commitment to inclusion & equality:

• One of the World’s Most Ethical Companies by Ethisphere
• Gender-Equality Index by Bloomberg
• Workplace Pride Global Benchmark
  
  

At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law.

We are committed to a culture of inclusion built upon our core value of respect.

Join us and be part of a company where you will feel included and empowered to succeed.

Seniority level

• Seniority level Not Applicable

Employment type

• Employment type Full-time

Job function

• Job function Engineering and Information Technology
• Industries IT Services and IT Consulting and Telecommunications

Referrals increase your chances of interviewing at Nokia by 2x

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Milpitas, CA 111,300.00- 189,200.00 2 weeks ago

Field Design Engineer (5G/4G/LTE) - Product Field Testing of Smartphones/Devices Senior Optical Mixed Signal Design Validation Engineer Senior Mixed Signal Design Validation Engineer

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Principal High Speed Mixed Signal Circuit Design Engineer

Join to apply for the Principal High Speed Mixed Signal Circuit Design Engineer role at Nokia

Principal High Speed Mixed Signal Circuit Design Engineer

2 days ago Be among the first 25 applicants

Join to apply for the Principal High Speed Mixed Signal Circuit Design Engineer role at Nokia

Job Description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The

Job Description

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise

Join Optical Networks division , where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.

How You Will Contribute And What You Will Learn

• Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs;
• Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary;
• Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc.
• Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality;
• Need to support and comply with the team’s design methodologies and release flows.
  
  

Key Skills And Experience

Mandatory Knowledge/Skills/Abilities:

• Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc.
• Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies.
• Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production.
• Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis;
• Must have a good understanding of device physics and the impacts of layout effects;
• Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS;
• Collaborative with other local or remote team members in a fast-paced professional environment.
  
  

Preferred Knowledge/Skill/Abilities:

• Fluent in verbal and written communications;
• Independently resolves issues and conquer design challenges;
• Self-motivated and detail-oriented;
• Has the knowledge of (optical) communication theories and Matlab coding.
  
  

Education and Experience Requirements:

• Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience
  
  

About Us

Come create the technology that helps the world act together

Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world.

We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work

What we offer

Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered.

Nokia is committed to inclusion and is an equal opportunity employer

Nokia has received the following recognitions for its commitment to inclusion & equality:

• One of the World’s Most Ethical Companies by Ethisphere
• Gender-Equality Index by Bloomberg
• Workplace Pride Global Benchmark
  
  

At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law.

We are committed to a culture of inclusion built upon our core value of respect.

Join us and be part of a company where you will feel included and empowered to succeed.

Seniority level

• Seniority level Not Applicable

Employment type

• Employment type Full-time

Job function

• Job function Engineering and Information Technology
• Industries IT Services and IT Consulting and Telecommunications

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High Speed Analog/Mixed-Signal IC Design Engineer

Austin, Texas, United States

Hardware

Summary

Posted: Oct 31, 2024

Role Number: 200576830

At Apple, our products are revolutionizing the way people live across the globe. Within our Analog-Mixed/Signal group, your role will be crucial in pushing the boundaries of what our technology can achieve. We are dedicated to crafting high-quality, innovative hard IPs that surpass the ordinary, adjusting to the escalating complexity of SOC/PHY designs and multiplying projects within tight production schedules. Our environment thrives on these challenges, fueled by a team of exceptional individuals passionate about continual learning and making a substantial impact. If you excel in dynamic settings, relish collaborative problem-solving, and seek to make a societal impact through your work, you might be the ideal candidate for our team. At Apple, you'll join a culture that encourages you to take ownership of your career, supported by colleagues committed to making a difference.

Description

In this role, you will leverage your expertise to develop cutting-edge circuits and architectures for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple's leadership in innovation and market presence, setting new standards in the tech industry.

Minimum Qualifications

• BSEE with at least 10 years of relevant experience

Preferred Qualifications

• Technical Expertise: Demonstrated proficiency in high-speed analog/mixed-signal architecture and circuit design, including frequency synthesizers, CDR, ADCs, DACs, RO/LC oscillators, regulators, on-chip sensors, compensation techniques, droop detection and recovery, and digitally-assisted analog techniques.

• Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.

• Simulation and Modeling: Skilled in designing/debugging RTL, developing System Verilog models, and performing behavioral simulations to explore new architectural performance and functions.

• Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving.

• Innovation and Learning: A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset.

• Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .

Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation.

Apple participates in the E-Verify program in certain locations as required by law.Learn more about the E-Verify program ( .

Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you're applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines applicable in your area.

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.