23 Timing jobs in the United States

CPU Design Timing Engineer

Austin, Texas, United States

Hardware

Summary

Posted: May 19, 2025

Role Number: 200605314

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!

In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with constructing and modify timing flows, timing analysis, and timing closure.

Description

As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:

• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency • Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience

• Experience working on timing for 1 ghz+ designs, including how to handle multiple clock and power domains

• Experience with one of the following static timing tools: Primetime or Tempus

• Experience with cross talk, noise, OCV, uncertainty, and derate methodology

• Experience with script writing and debugging in one or more of the following languages: TCL, Perl, Python

Preferred Qualifications

• Implementation experience on high performance CPU designs

• Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs

• Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)

• Knowledge of static timing tools and flows including how to handle multiple clock and power domains

• Knowledge of device physics especially aspects which impact timing: cross talk, noise, OCV, uncertainty and derate methodology

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .

Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation.

Apple participates in the E-Verify program in certain locations as required by law.Learn more about the E-Verify program ( .

Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines applicable in your area.

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

CPU Design Timing Engineer

Beaverton, Oregon, United States

Hardware

Summary

Posted: Apr 10, 2025

Role Number: 200598926

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!

In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.

Description

As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project.

Responsibilities include but are not limited to: • Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.

Minimum Qualifications

• Minimum BS and 10+ years of relevant experience

• Experience with timing analysis

• Experience with a static timing analysis tool such as PrimeTime® or Tempus®

• Experience with TCL and either Perl or Python

Preferred Qualifications

• Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs

• Understanding of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence

• Understanding of deep sub-micron technologies and scaling trends

• Working knowledge of CPU microarchitecture including common fundamental timing paths

• Working knowledge of clock-domain crossing and reset-domain crossing

• Experience with with multiple clock and power domains

• Experience with SDC command usage including clock definitions, timing exceptions, and IO constraints

• Experience with noise analysis and fixing noise in designs

• Experience with variation modeling in static timing analysis tools

• Experience with RTL modeling and assertion based verification

• Experience with data parsing, analysis, and representation/plotting

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant ( .

Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation.

Apple participates in the E-Verify program in certain locations as required by law.Learn more about the E-Verify program ( .

Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more .

Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines applicable in your area.

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Minimum qualifications:
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 2 years of experience in static timing analysis.
+ Experience in Primetime or Tempus Tcl scripting and static timing analysis debug and problem solving.
+ Experience in sub chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.
Preferred qualifications:
+ Experience writing, reviewing and verifying complex Tcl constraints for static timing analysis.
+ Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
+ Experience working with multiple foundries.
+ Knowledge of semiconductor device physics and transistor characteristics.
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will work on the physical implementation of ASICs using advanced technology nodes. You will work on constraint development and validation, and timing closure of large, complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. You will perform technical evaluations of vendors, tools, methodologies, and will provide recommendations. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to understand and implement the requirements.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google ( .
+ Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
+ Perform sub chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
+ Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.
+ Own and maintain Primetime STA flows.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also and If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form:

**Summary:**
Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.
**Required Skills:**
ASIC Implementation Engineer - Timing Responsibilities:
1. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks
2. Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes
3. Perform STA for full chip and Physical partition blocks using PrimeTime
4. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
5. Developing Automation scripts and Methodology for all FE-tools including ( Synthesis, STA)
6. Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback
**Minimum Qualifications:**
Minimum Qualifications:
7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8. 6+ years of experience with STA tools
9. Experience with developing full chip flat & hierarchical timing constraints
10. Experience with AOCV/POCV timing analysis , SI noise analysis
11. Experience with running Static Timing Analysis for full chip using DMSA
12. Knowledge of front-end and back-end ASIC flows
13. Experience with communicating across functional internal teams and vendors
**Preferred Qualifications:**
Preferred Qualifications:
14. Experience with SOC Design Integration & Front End Implementation
15. Experience with Front End Synthesis tools such as Design Compiler, Genus
16. Experience with Back End PD tools such as Fusion Compiler, Innovus
17. Experience with Understanding RTL design using SystemVerilog or other HDL
18. Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows
19. Knowledge of Timing/physical libraries, SRAM Memories
**Public Compensation:**
$142,000/year to $203,000/year + bonus + equity + benefits
**Industry:** Internet
**Equal Opportunity:**
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at

**Summary:**
Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.
**Required Skills:**
ASIC Implementation Engineer - Timing Responsibilities:
1. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks
2. Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes
3. Perform STA for full chip and Physical partition blocks using PrimeTime
4. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
5. Developing Automation scripts and Methodology for all FE-tools including ( Synthesis, STA)
6. Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback
**Minimum Qualifications:**
Minimum Qualifications:
7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8. 6+ years of experience with STA tools
9. Experience with developing full chip flat & hierarchical timing constraints
10. Experience with AOCV/POCV timing analysis , SI noise analysis
11. Experience with running Static Timing Analysis for full chip using DMSA
12. Knowledge of front-end and back-end ASIC flows
13. Experience with communicating across functional internal teams and vendors
**Preferred Qualifications:**
Preferred Qualifications:
14. Experience with SOC Design Integration & Front End Implementation
15. Experience with Front End Synthesis tools such as Design Compiler, Genus
16. Experience with Back End PD tools such as Fusion Compiler, Innovus
17. Experience with Understanding RTL design using SystemVerilog or other HDL
18. Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows
19. Knowledge of Timing/physical libraries, SRAM Memories
**Public Compensation:**
$142,000/year to $203,000/year + bonus + equity + benefits
**Industry:** Internet
**Equal Opportunity:**
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > CPU Engineering

General Summary:

NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

About The Role:

In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.

Key Responsibilities:

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.

• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.

• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.

• Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.

• Evaluate multiple timing methodologies/tools on different designs and technology nodes.

• Work on automation scripts within STA/PD tools for methodology development.

• Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment

• Strong experience in design automation using TCL/Perl/Python.

• Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

OR

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

OR

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Preferred Qualification/Skills

• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

• Hands-on experience with STA tools - Prime-time, Tempus

• Have experience in driving timing convergence at Chip-level and Hard-Macro level

• In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

• Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)

• Expert in scripting languages – TCL, Perl, Python

• Basic knowledge of device physics

This position is open to Austin, Folsom and Santa Clara. The compensation will be based on location.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here ( . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits :

$148,300.00 - $222,500.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link .

If you would like more information about this role, please contact Qualcomm Careers ( .

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification

**Company:**
Qualcomm Technologies, Inc.
**Job Area:**
Engineering Group, Engineering Group > CPU Engineering
**General Summary:**
NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.
**About The Role:**
In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.
Key Responsibilities:
+ STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
+ Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
+ Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
+ Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.
+ Evaluate multiple timing methodologies/tools on different designs and technology nodes.
+ Work on automation scripts within STA/PD tools for methodology development.
+ Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
+ Strong experience in design automation using TCL/Perl/Python.
+ Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
**Minimum Qualifications:**
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Preferred Qualification/Skills
+ Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
+ Hands-on experience with STA tools - Prime-time, Tempus
+ Have experience in driving timing convergence at Chip-level and Hard-Macro level
+ In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
+ Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
+ Expert in scripting languages - TCL, Perl, Python
+ Basic knowledge of device physics
This position is open to Austin, Folsom and Santa Clara. The compensation will be based on location.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here ( . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
**To all Staffing and Recruiting Agencies** : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
**EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.**
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
**Pay range** **and Other Compensation & Benefits** **:**
$148,300.00 - $222,500.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link .
If you would like more information about this role, please contact Qualcomm Careers ( .
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification

**Company:**
Qualcomm Technologies, Inc.
**Job Area:**
Engineering Group, Engineering Group > CPU Engineering
**General Summary:**
NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.
**About The Role:**
In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.
Key Responsibilities:
+ STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
+ Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
+ Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
+ Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.
+ Evaluate multiple timing methodologies/tools on different designs and technology nodes.
+ Work on automation scripts within STA/PD tools for methodology development.
+ Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
+ Strong experience in design automation using TCL/Perl/Python.
+ Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
**Minimum Qualifications:**
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Preferred Qualification/Skills
+ Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
+ Hands-on experience with STA tools - Prime-time, Tempus
+ Have experience in driving timing convergence at Chip-level and Hard-Macro level
+ In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
+ Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
+ Expert in scripting languages - TCL, Perl, Python
+ Basic knowledge of device physics
This position is open to Austin, Folsom and Santa Clara. The compensation will be based on location.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here ( . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
**To all Staffing and Recruiting Agencies** : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
**EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.**
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
**Pay range** **and Other Compensation & Benefits** **:**
$148,300.00 - $222,500.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link .
If you would like more information about this role, please contact Qualcomm Careers ( .
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification

**Company:**
Qualcomm Technologies, Inc.
**Job Area:**
Engineering Group, Engineering Group > CPU Engineering
**General Summary:**
NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.
**About The Role:**
In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.
Key Responsibilities:
+ STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
+ Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
+ Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
+ Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.
+ Evaluate multiple timing methodologies/tools on different designs and technology nodes.
+ Work on automation scripts within STA/PD tools for methodology development.
+ Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
+ Strong experience in design automation using TCL/Perl/Python.
+ Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
**Minimum Qualifications:**
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Preferred Qualification/Skills
+ Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
+ Hands-on experience with STA tools - Prime-time, Tempus
+ Have experience in driving timing convergence at Chip-level and Hard-Macro level
+ In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
+ Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
+ Expert in scripting languages - TCL, Perl, Python
+ Basic knowledge of device physics
This position is open to Austin, Folsom and Santa Clara. The compensation will be based on location.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here ( . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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**EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.**
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
**Pay range** **and Other Compensation & Benefits** **:**
$148,300.00 - $222,500.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link .
If you would like more information about this role, please contact Qualcomm Careers ( .
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification