17 Timing jobs in the United States

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

• You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level.

• Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.

• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

What we need to see:

• Great teammate

• BS (or equivalent experience) in Electrical or Computer Engineering

• 8+ years experience or MS (or equivalent experience) with 2 years experience in Synthesis and Timing.

• Understanding of DFT logic and hands-on experience in design closure.

• Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

• Knowledge in process variation effect modeling and experience in design convergence taking into account process variations.

• Experience in critical path planning and crafting needed.

• Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus.

• Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

• Proficiency in Python, Tcl and Make for automation and scripting tasks.

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

You will also be eligible for equity and benefits .

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

• You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level.

• Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets.

• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

What we need to see:

• Great teammate

• BS (or equivalent experience) in Electrical or Computer Engineering

• 8+ years experience or MS (or equivalent experience) with 2 years experience in Synthesis and Timing.

• Understanding of DFT logic and hands-on experience in design closure.

• Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

• Knowledge in process variation effect modeling and experience in design convergence taking into account process variations.

• Experience in critical path planning and crafting needed.

• Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus.

• Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

• Proficiency in Python, Tcl and Make for automation and scripting tasks.

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

You will also be eligible for equity and benefits .

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company. What you will be doing: You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. What we need to see: Great teammate BS (or equivalent experience) in Electrical or Computer Engineering 8 years experience or MS (or equivalent experience) with 2 years experience in Synthesis and Timing. Understanding of DFT logic and hands-on experience in design closure. Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. Knowledge in process variation effect modeling and experience in design convergence taking into account process variations. Experience in critical path planning and crafting needed. Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus. Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence. Proficiency in Python, Tcl and Make for automation and scripting tasks. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until October 4, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.aa415a4b-8b21-40fc-a65c-70d2b25ca29a

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company. What you will be doing: You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. What we need to see: Great teammate BS (or equivalent experience) in Electrical or Computer Engineering 8 years experience or MS (or equivalent experience) with 2 years experience in Synthesis and Timing. Understanding of DFT logic and hands-on experience in design closure. Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. Knowledge in process variation effect modeling and experience in design convergence taking into account process variations. Experience in critical path planning and crafting needed. Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus. Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence. Proficiency in Python, Tcl and Make for automation and scripting tasks. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until October 4, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.aa415a4b-8b21-40fc-a65c-70d2b25ca29a

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company. What you will be doing: You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at block level, cluster level, and/or full chip level. Analyze and optimize design constraints and synthesis parameters to achieve performance, power, and area targets. Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. What we need to see: Great teammate BS (or equivalent experience) in Electrical or Computer Engineering 8 years experience or MS (or equivalent experience) with 2 years experience in Synthesis and Timing. Understanding of DFT logic and hands-on experience in design closure. Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. Knowledge in process variation effect modeling and experience in design convergence taking into account process variations. Experience in critical path planning and crafting needed. Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus. Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence. Proficiency in Python, Tcl and Make for automation and scripting tasks. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits . Applications for this job will be accepted at least until October 4, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.aa415a4b-8b21-40fc-a65c-70d2b25ca29a

• Designs and optimizes traffic signal timings and phasing plans to maximize efficiency and minimize delays.
• Performs modifications and upgrades to traffic signal controller databases using system software and traffic modeling using Synchro and Tru-Traffic software.
• Monitors system capacity and flow, identifies, and reports/repairs minor communications/computing system problems.
• Diagnoses incidents and provides coordinated quick responses to traffic and incident problems by working closely with appropriate agencies.
• Maintains computerized databases of traffic signal timings.
• Evaluates system-wide signal interconnect network expansion feasibility along arterials and collectors.
• Performs engineering review and data analysis, develop engineering reports and associated documents (work orders, traffic regulations, signal operating plans, benefit/cost analysis, etc.). This includes field assessments, application of engineering principles and judgment to identify operational and safety deficiencies and the development of appropriate remedial action.
• Prepares plans and documents for the Traffic Operations Manager to sign and seal engineering as required.
• Provides review comments on plan submittals generated by the Department and other entities.
• Ability to lift and/or move up to 25 pounds.
• Performs other related duties as required.

• Knowledge of traffic engineering principles and practices.
• Knowledge of traffic operations analysis and study techniques.
• Knowledge of FDOT Design Standards.
• Knowledge of traffic signal timing and phasing.
• Knowledge of the operation of an adaptive traffic control system utilizing CENTRACS, or the ability to learn the task.
• Knowledge of the use of Synchro, or the ability to learn the task.
• Skill in effective oral and written communications.
• Skill in use of personal computers and ability to use Microsoft Office® (Word, Excel, PowerPoint, & Outlook).
• Skilled in interpreting and disseminating traffic engineering-related data.
• Ability to collect, analyze, and interpret engineering data.
• Ability to manage workload to produce on time resolutions to problems.
• Ability to effectively supervise others.

• Florida Retirement System (FRS) retirement plan
• PTO (Paid Time Off)
• Paid holidays
• Group insurance
• Tuition reimbursement
• Deferred compensation
• Medical leave pool
• Annual medical leave buy-back
• Mid-management/Professional grade, and management personnel may receive 40 hours of admin leave per calendar year.

• Acknowledge
• Decline

• Yes
• No

• No
• Yes

• GED
• High School
• Associate degree
• Bachelor's Degree
• Master's Degree
• Doctorate
• None of the above

• Ten or more years of experience
• Nine years but less than ten
• Eight years but less than nine
• Seven years but less than eight
• Six years but less than seven
• Five years but less than six
• Four years but less than five
• Three years but less than four
• Two years but less than three
• One year but less than two
• Less than one year of experience

• No
• Yes

• Yes
• No

• Yes
• No

• Acknowledged
• Declined

• Yes
• No

• Yes
• No

• Billboard
• Facebook
• Friend/Family Referral
• Indeed
• Job Fair
• LinkedIn
• Magazine publication
• Pasco County employee
• Pasco County Traffic Sign
• Utility bill insert
• Pasco County website/Governmentjobs.com
• Other

Valvetrain & Timing Drive Design Release Engineer is responsible for engineering activities related to development of Valvetrain and Timing Drive components for gasoline engines. Activities include design, development, testing, manufacturing interface, and failure analysis.  The release engineer will be a part of a team of engineers for problem solving, product improvement, cost reduction and other issues as needed.    The Release Engineer will interact with all areas of the FCA that touch the release of a component. This will include Purchasing, Supplier Quality, Engine Plants, Design Group, and Parts & Service. Some travel to engine plants and suppliers is required. The Design Release Engineer must be a motivated self-starter, willing to work in a fast-paced environment. 

Essential Functions: 

• Participates as a team member on various engineering projects.  Must be a team player able to manage multiple priorities while considering the inputs from a variety of stakeholders. 
• Resolves technical issues based on engineering analysis of camshafts, camshaft phasers, rocker arms, valves, valve seat & valve guide inserts, valve springs, timing chains, timing guides, and tensioners. 
• Plan and coordinate test execution (through utilization of engineering tools such as DFMEA’s and DVP&R) and monitor progress and results. 
• Analyzes test and measurement data creating summaries with data-based conclusions and makes recommendations to the team. 

Our Benefits - Designed with You in Mind

Comprehensive Health & Well-being Coverage

From your very first day, you’ll have access to medical, dental, vision, and prescription drug coverage - ensuring you and your family stay healthy and protected.

Generous Paid Time Off

We believe in work-life balance. That’s why we offer: 17+ paid holidays, including shut-down from December 24th through New Years Day every year. Vacation, float & wellbeing days, sick time and fully paid parental leave when your family needs you most.

Competitive Retirement Savings Plans

We help you plan for the future with:

• An employer match on contributions to your 401k, Roth, and Catch-Up plans
• An employer contribution, even if you don’t contribute

Income Protection & Insurance Options

Benefit from included and optional disability, life, and other insurance programs - because your peace of mind matters.

Company Vehicle Lease Program

Eligible employees and their immediate families can enjoy company vehicle lease options with included insurance, maintenance, and unlimited mileage. Plus, take advantage of exclusive discounts on Stellantis products.

Family Building Benefit

We proudly support all paths to parenthood- including fertility and infertility treatments, adoption services, and gestational surrogacy.

Support for Your Growth and Giving Back

We believe in investing in your future and your passions:

• Tuition reimbursement
• Student loan refinancing programs
• 18 paid volunteer hours each year to make a difference in your community

And so much more!

When you join us, you’re not just building a career - you’re joining a company that supports you, inside and outside of work.