3,905 Verification Engineer jobs in the United States
Verification Engineer
Posted today
Job Viewed
Job Description
Responsibilities
+ Establish the verification strategy and approach.
+ Lead verification reviews of system requirements.
+ Develop and maintain a Requirements Traceability and Verification Matrix (RVTM).
+ Engage with community IPTs, Working Groups, and Communities of Practice.
+ Attend customer staff meetings and frequently meet with customer technical leads.
+ Support Systems Engineering technical reviews.
+ Mentor junior engineers.
+ Execute and improve the Verification strategy and approach.
+ Develop technical documentation, data, presentations, and white paper submissions for approval.
+ Lead small teams executing verification activities on sub-program requirements.
+ Deliver engineering products and develop innovative solutions to complex mission and business challenges.
+ Present content and support discussions with Navy customers/clients to solve technical problems and implement solutions.
Essential Skills
+ Bachelor's Degree in Engineering, Science, or related field, and 6 years of related/relevant work or a Master's Degree and 4 years of related/relevant work.
+ Model Based Systems Engineering experience including SysML and DOORS/DXL.
+ Experience spanning the SE Lifecycle with an emphasis on integration, verification, and validation.
+ Proficiency with engineering tools and languages such as No Magic Products, PTC Windchill, IBM DOORS, SysML, JAVA, and/or MATLAB Simulink.
+ Strong interpersonal skills to interact with diverse work teams.
+ Proficiency in Microsoft Office tools.
Additional Skills & Qualifications
+ Management Professional (PMP) certification.
+ Associate Systems Engineering Professional (ASEP) INCOSE certification.
Pay and Benefits
The pay range for this position is $58.00 - $84.00/hr.
Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:
- Medical, dental & vision - Critical Illness, Accident, and Hospital - 401(k) Retirement Plan - Pre-tax and Roth post-tax contributions available - Life Insurance (Voluntary Life & AD&D for the employee and dependents) - Short and long-term disability - Health Spending Account (HSA) - Transportation benefits - Employee Assistance Program - Time Off/Leave (PTO, Vacation or Sick Leave)
Workplace Type
This is a hybrid position in Rockville,MD.
Application Deadline
This position is anticipated to close on Oct 22, 2025.
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing due to a disability, please email (% ) for other accommodation options.
Design Verification Engineer
Posted today
Job Viewed
Job Description
Position Title: Design Verification Engineer
Location: San Jose, CA (Hybrid – 2–3 days onsite)
Clearance Requirements: None
Position Status: Contract
Pay Rate: $75/hr on W2
Position Description:
Seneca Resources is seeking a highly skilled and self-motivated Design Verification Engineer to join a cutting-edge team driving the development of industry-leading IP for next-generation processors. This role offers the opportunity to work on complex digital architectures and collaborate across RTL, firmware, circuit, and architecture teams to deliver high-performance, high-quality solutions.
This is a hybrid role with flexibility for remote work, ideally aligned to the Pacific Time Zone. Candidates must be available for video-based technical interviews and comfortable being on camera.
Key Responsibilities:
Develop and maintain functional verification tests for complex digital designs
Build directed and random test cases; debug failures and identify root causes
Collaborate with RTL and firmware engineers to resolve design defects
Perform functional and code coverage analysis
Provide technical support across engineering teams
Contribute to verification planning and execution for high-speed memory interfaces and processor subsystems
Required Skills/Education:
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related field
10+ years of experience in ASIC design verification
Proficiency in Verilog, SystemVerilog, and UVM
Strong programming skills in C/C++
Experience with DDR, Memory Controller, or PHY verification
Familiarity with scripting languages such as Python, Perl, or TCL
Experience debugging RTL and firmware using simulation tools
Understanding of Design for Test (DFT) methodologies is a plus
Strong analytical, problem-solving, and communication skills
Ability to work effectively across distributed teams and time zones
About Seneca Resources
At Seneca Resources, we are more than just a staffing and consulting firm—we are a trusted career partner. With offices across the U.S. and clients ranging from Fortune 500 companies to government organizations, we provide opportunities that help professionals grow their careers while making an impact.
When you work with Seneca, you’re choosing a company that invests in your success, celebrates your achievements, and connects you to meaningful work with leading organizations nationwide.
Modeling/Verification Engineer
Posted today
Job Viewed
Job Description
Position Title: SystemC Modeling & Verification Engineer
Location: Austin, TX (Hybrid)
Clearance Requirements: None
Position Status: Contract
Pay Rate: $60-65/hr on W2
Seneca Resources is seeking a highly skilled and detail-oriented SystemC Modeling & Verification Engineer to join a cutting-edge team developing performance models for next-generation ASICs and system-level designs. This role is ideal for engineers with deep expertise in SystemC/TLM2, C/C++, and functional verification, who thrive in collaborative environments and are passionate about optimizing hardware simulation accuracy and performance.
You’ll work closely with architecture, firmware, and hardware teams to build cycle-approximate models, validate functionality, and integrate your work into AMD’s internal tools and workflows.
Key Responsibilities:
Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects
Integrate models into AMD system-level design tools and ensure performance alignment
Identify and resolve bottlenecks in simulation models to meet design specifications
Create and execute testbenches for model validation and participate in system-level debugging
Produce clear documentation including usage guidelines, design specifications, and performance metrics
Deliver cycle-approximate performance models and support SV/UVM-based functional and performance verification
Required Skills/Education:
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related field
5+ years of experience in ASIC modeling and verification or software/firmware development in a hardware setting
Strong proficiency in C/C++ development within a Linux environment
Experience with SystemC, Verilog, SystemVerilog, and verification libraries such as UVM
Familiarity with debug tools like GDB and Valgrind
Knowledge of Perl, Makefiles, and scripting for automation
Experience with DPI/PLI integration between C and Verilog environments
Strong analytical skills and attention to detail
Excellent written and verbal communication skills
Preferred knowledge of PCIe, AXI, and system interconnect protocols
About Seneca Resources
At Seneca Resources, we are more than just a staffing and consulting firm—we are a trusted career partner. With offices across the U.S. and clients ranging from Fortune 500 companies to government organizations, we provide opportunities that help professionals grow their careers while making an impact.
When you work with Seneca, you’re choosing a company that invests in your success, celebrates your achievements, and connects you to meaningful work with leading organizations nationwide
We are an Equal Opportunity Employer and strongly encourage individuals of all races, ethnicities, genders, abilities, and backgrounds to apply.
Board Verification Engineer
Posted today
Job Viewed
Job Description
Position Title: Board Verification Engineer
Location: Austin, TX (100% Onsite; limited remote flexibility with manager approval)
Clearance Requirements: None
Position Status: Contract
Pay Rate:$65/hr on w2
Position Description
We are seeking a Board Verification Engineer to join our team in Austin, TX. In this role, you will play a critical part in validating next-generation datacenter GPU platforms through both pre-silicon and post-silicon board-level verification. You will collaborate with cross-functional teams spanning hardware, firmware, and software to ensure robust system performance, power integrity, and compliance with industry standards.
This is a hands-on engineering position where you will leverage your expertise in power electronics, FPGA/CPLD development, high-speed interface characterization, and test automation to drive innovation and deliver reliable solutions. If you thrive in a fast-paced environment and enjoy solving complex technical challenges, this opportunity is for you.
Key Responsibilities
- Define, develop, and execute board-level validation test plans for datacenter GPU platforms (pre-silicon and post-silicon).
- Develop platform validation flows to ensure comprehensive end-to-end coverage.
- Implement debug strategies to resolve issues across all phases of the program.
- Collaborate with hardware, firmware, and software teams on design requirements, risk assessments, and system tradeoffs.
- Conduct laboratory testing of new designs to verify compliance with specifications.
- Support board/system issues during characterization and product launch phases.
- Utilize dashboards to track execution tasks, issues, design changes, and lessons learned.
- Review converter topologies and select appropriate power components (PWM controllers, transistors, magnetics, capacitors).
- Provide concise technical updates and recommendations to management.
Required Skills/Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- Strong understanding of power electronics, especially multiphase power converters.
- Hands-on experience with oscilloscopes, multi-meters, current probes, electronic loads, and protocol analyzers.
- Proficiency in documenting experimental results in a structured, repeatable format.
- Experience with hardware, firmware, and system-level interfaces.
- Proficiency with circuit simulation tools (PSPICE, LTSPICE, SIMPLIS).
- Knowledge of FPGA/CPLD development and schematic capture/circuit design.
- Expertise in power and signal integrity analysis.
- Familiarity with low-speed protocols (I2C, SPI, I3C, SVI2, SVI3) and high-speed protocols (PCIe Gen5).
- Experience with high-speed interface characterization.
- Test automation skills using Python, Perl, Tcl, or LabView.
- Strong analytical, communication, and collaboration skills.
- Ability to thrive in a dynamic, team-oriented environment and independently drive tasks to completion.
- Leadership and mentoring experience is a plus.
About Seneca Resources
At Seneca Resources, we are more than just a staffing and consulting firm—we are a trusted career partner. With offices across the U.S. and clients ranging from Fortune 500 companies to government organizations, we provide opportunities that help professionals grow their careers while making an impact.
When you work with Seneca, you’re choosing a company that invests in your success, celebrates your achievements, and connects you to meaningful work with leading organizations nationwide.
Seneca Resources is proud to be an Equal Opportunity Employer, committed to fostering a diverse and inclusive workplace where all qualified individuals are encouraged to apply.
Design Verification Engineer
Posted today
Job Viewed
Job Description
_corporate_fare_ Google _place_ Mountain View, CA, USA
**Mid**
Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
**Minimum qualifications:**
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 4 years of experience in silicon design verification.
+ Experience developing and maintaining verification testbenches, test cases, and test environments.
**Preferred qualifications:**
+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
+ Experience in low-power design verification.
**About the job**
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more aboutbenefits at Google ( .
**Responsibilities**
+ Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
+ Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with Stored Value Account (SVA) and industry leading formal tools.
+ Identify and write all types of coverage measures for stimulus and corner-cases.
+ Debug tests with design engineers to deliver functionally correct design blocks.
+ Manage coverage measures to identify verification holes and to show progress towards tape-out.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google'sApplicant and Candidate Privacy Policy (./privacy-policy) .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See alsoGoogle's EEO Policy ( ,Know your rights: workplace discrimination is illegal ( ,Belonging at Google ( , andHow we hire ( .
If you have a need that requires accommodation, please let us know by completing ourAccommodations for Applicants form ( .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also and If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form:
Senior Verification Engineer
Posted today
Job Viewed
Job Description
As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume, with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud AI & Advanced Systems Engineering (CAASE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing-improving planning, quality, delivery, scale, and sustainability across Microsoft cloud hardware.
We are seeking a motivated **Senior** **Verification Engineer** who is enthusiatic about cutting-edge hardware acceleration and eager to translate this interest into commercial reality through Azure cloud services reaching thousands of customers and millions of servers.
**Responsibilities**
+ Verify IP blocks for Microsoft's next-generation cloud servers using FPGA and ASIC technologies.
+ Collaborate with cross-functional teams to develop and validate IP for hardware acceleration platforms.
+ Analyze complex verification challenges and drive creative, scalable solutions across simulation and debug workflows.
+ Contribute to the development of reusable verification infrastructure and methodologies.
+ Support pre-silicon validation efforts to enable early software development and hardware-software co-debug.
**Qualifications**
**Required Qualifications:**
+ Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience
+ OR equivalent experience.
+ 4+ years of verification experience.
+ 3 years of developing UVM-based testbenches or completion of formal design verification (DV) training.
**Other Requirements:**
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
**Preferred Qualifications:**
+ Experience as a technical team lead in verification or hardware development projects.
+ Proficiency in Python and/or Perl for scripting and automation.
+ Experience with FPGA design, implementation, and debug tools.
+ Expereince in leveraging Copilot or LLM-based tools to enhance productivity and verification workflows.
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $34,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD 158,400 - 258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: will accept applications for the role until October 14th, 2025.
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations ( .
Senior Verification Engineer
Posted today
Job Viewed
Job Description
As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume, with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud AI & Advanced Systems Engineering (CAASE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing-improving planning, quality, delivery, scale, and sustainability across Microsoft cloud hardware.
We are seeking a motivated **Senior** **Verification Engineer** who is enthusiatic about cutting-edge hardware acceleration and eager to translate this interest into commercial reality through Azure cloud services reaching thousands of customers and millions of servers.
**Responsibilities**
+ Verify IP blocks for Microsoft's next-generation cloud servers using FPGA and ASIC technologies.
+ Collaborate with cross-functional teams to develop and validate IP for hardware acceleration platforms.
+ Analyze complex verification challenges and drive creative, scalable solutions across simulation and debug workflows.
+ Contribute to the development of reusable verification infrastructure and methodologies.
+ Support pre-silicon validation efforts to enable early software development and hardware-software co-debug.
**Qualifications**
**Required Qualifications:**
+ Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience
+ OR equivalent experience.
+ 4+ years of verification experience.
+ 3 years of developing UVM-based testbenches or completion of formal design verification (DV) training.
**Other Requirements:**
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
**Preferred Qualifications:**
+ Experience as a technical team lead in verification or hardware development projects.
+ Proficiency in Python and/or Perl for scripting and automation.
+ Experience with FPGA design, implementation, and debug tools.
+ Expereince in leveraging Copilot or LLM-based tools to enhance productivity and verification workflows.
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $34,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD 158,400 - 258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: will accept applications for the role until October 14th, 2025.
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations ( .
Be The First To Know
About the latest Verification engineer Jobs in United States !
Senior Verification Engineer
Posted today
Job Viewed
Job Description
As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume, with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud AI & Advanced Systems Engineering (CAASE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing-improving planning, quality, delivery, scale, and sustainability across Microsoft cloud hardware.
We are seeking a motivated **Senior** **Verification Engineer** who is enthusiatic about cutting-edge hardware acceleration and eager to translate this interest into commercial reality through Azure cloud services reaching thousands of customers and millions of servers.
**Responsibilities**
+ Verify IP blocks for Microsoft's next-generation cloud servers using FPGA and ASIC technologies.
+ Collaborate with cross-functional teams to develop and validate IP for hardware acceleration platforms.
+ Analyze complex verification challenges and drive creative, scalable solutions across simulation and debug workflows.
+ Contribute to the development of reusable verification infrastructure and methodologies.
+ Support pre-silicon validation efforts to enable early software development and hardware-software co-debug.
**Qualifications**
**Required Qualifications:**
+ Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience
+ OR equivalent experience.
+ 4+ years of verification experience.
+ 3 years of developing UVM-based testbenches or completion of formal design verification (DV) training.
**Other Requirements:**
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
**Preferred Qualifications:**
+ Experience as a technical team lead in verification or hardware development projects.
+ Proficiency in Python and/or Perl for scripting and automation.
+ Experience with FPGA design, implementation, and debug tools.
+ Expereince in leveraging Copilot or LLM-based tools to enhance productivity and verification workflows.
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $34,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD 158,400 - 258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: will accept applications for the role until October 14th, 2025.
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations ( .
Senior Verification Engineer
Posted today
Job Viewed
Job Description
As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume, with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud AI & Advanced Systems Engineering (CAASE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing-improving planning, quality, delivery, scale, and sustainability across Microsoft cloud hardware.
We are seeking a motivated **Senior** **Verification Engineer** who is enthusiatic about cutting-edge hardware acceleration and eager to translate this interest into commercial reality through Azure cloud services reaching thousands of customers and millions of servers.
**Responsibilities**
+ Verify IP blocks for Microsoft's next-generation cloud servers using FPGA and ASIC technologies.
+ Collaborate with cross-functional teams to develop and validate IP for hardware acceleration platforms.
+ Analyze complex verification challenges and drive creative, scalable solutions across simulation and debug workflows.
+ Contribute to the development of reusable verification infrastructure and methodologies.
+ Support pre-silicon validation efforts to enable early software development and hardware-software co-debug.
**Qualifications**
**Required Qualifications:**
+ Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience
+ OR equivalent experience.
+ 4+ years of verification experience.
+ 3 years of developing UVM-based testbenches or completion of formal design verification (DV) training.
**Other Requirements:**
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
**Preferred Qualifications:**
+ Experience as a technical team lead in verification or hardware development projects.
+ Proficiency in Python and/or Perl for scripting and automation.
+ Experience with FPGA design, implementation, and debug tools.
+ Expereince in leveraging Copilot or LLM-based tools to enhance productivity and verification workflows.
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $34,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD 158,400 - 258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: will accept applications for the role until October 14th, 2025.
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations ( .
IC Verification Engineer
Posted 1 day ago
Job Viewed
Job Description
**1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)**
**2. If you already have a Candidate Account, please Sign-In before you apply.**
**Job Description:**
**Job duties include:**
· Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.
· Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology
· Build pseudo-random tests to verify and get to full Functional coverage
· Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps
· Document verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture.
· Drive improvements in Verification in terms of quality and efficiency.
**Requirements:**
· Bachelor's degree in Electrical Engineering or related degree and 8+ years related experience or Master's degree in Electrical Engineering or related degree and 6+ years related experience
· Experience writing and debugging complex test benches
· Must have a good understanding of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage.
· Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM
· Should have exceptionally good command over fundamental OOP principles.
· A good understanding of a complex protocol like PCIe or other multi-layered protocol will be a plus
· Capability to work independently and deliver.
· Knowledge of PCI Express protocol preferred
**Additional Job Description:**
**Compensation and Benefits**
The annual base salary range for this position is $120,000 - $192,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.**
**If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**
Welcome! Thank you for your interest in Broadcom!
We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.
For more information please visit our video library ( and check out our Connected by Broadcom ( series.
Follow us on Linked In Broadcom Inc ( .